Plasma induced depletion of fluorine from surfaces of fluorinated low-k dielectric materials
A low dielectric constant material having a first fluorine concentration in a near-surface portion and a second fluorine concentration in an interior portion provides an insulator suitable for use in integrated circuits. In a further aspect of the present invention, fluorine is depleted from a near-surface portion of a fluorine containing dielectric material by a reducing plasma. Fluorine in fluorinated low-k dielectric materials, such as SiOF, amorphous fluorinated carbon (a-F:C) and parylene-AF4, can react with surrounding materials such as metals and Si 3 N 4 , causing blisters and delamination. Treatment of these fluorinated low-k dielectric materials in a reducing plasma, which may be produced from precursor gases such as H 2 or NH 3 , depletes the surface region of fluorine and hence reduces reaction with surrounding materials and F outgassing. By selecting an appropriate point in the integration flow, specific interfaces which are most susceptible to F-attack can be targeted for depletion.
1. A method of forming an interlayer dielectric in an integrated circuit, comprising:
depositing a fluorinated material on a substrate, the fluorinated material having a top surface,
forming via openings in the fluorinated material, wherein the via openings define sidewalls;
forming a fluorine depleted top surface and fluorine depleted sidewalls by exposing the fluorinated material to a hydrogen containing plasma in a reaction chamber, wherein the plasma is formed in a chamber remote from the reaction chamber containing the fluorinated material;
forming a layer of a conductive material over the fluorine depleted sidewalls; and
forming an etch stop layer over the fluorine depleted top surface.
2. The method of claim 1 , wherein the fluorinated material is selected from the group consisting of a-C:F, parylene AF4, carbon-doped SiOF, fluorinated organic polymers, fluorinated siloxane polymers, and SiOF.
3. The method of claim 2 , further comprising depositing a conductive material in the via openings.
4. The method of claim 2 , wherein the fluorinated material comprises parylene-AF4.
5. The method of claim 1 , wherein forming the etch stop layer comprises forming a layer of silicon nitride over the fluorine depicted top surfaces.
6. The method of claim 1 , wherein the plasma is formed in a reaction chamber from ammonia and argon at a pressure between 1 mTorr and 50 Torr and an RF power of between 100 watts and 500 watts.
7. The method of claim 6 , wherein the ammonia is passed into the reaction chamber at a flow rate in the range of 10 sccm to 3 liters/minute.
8. The method of claim 1 , wherein the etch stop layer comprises silicon nitride.
9. A method of forming a dielectric, comprising:
depositing a material on a substrate, wherein the material is selected from the group consisting of a-C:F parylene AF4, carbon-doped SiOF, fluorinated organic polymers, and fluorinated siloxane polymers, the material having a top surface;
forming via openings in the material, wherein the via openings define sidewalls;
forming a fluorine depleted lop surface and fluorine depleted sidewalks by exposing the material to a reducing plasma in a reaction chamber, wherein the reducing plasma is formed in a chamber remote from the chamber containing the material;
forming a layer of a conductive material over the fluorine depleted sidewalls; and
forming an etch stop layer over the fluorine depleted top surface.
10. The method of claim 9 , further comprising depositing a conductive material in the via openings.
11. The method of claim 9 , wherein the material comprises parylene-AF4.
12. The method of claim 9 , wherein forming the etch stop layer comprises forming a layer of silicon nitride over the fluorine depleted top surface.
13. The method of claim 9 , wherein the plasma is formed in a reaction chamber from ammonia and argon at a pressure between 1 mTorr and 50 Torr and an RF power of between 100 watts and 500 watts.
14. The method of claim 13 , wherein the ammonia is passed into the reaction chamber at a flow rate in the range of 10 sccm to 3 liters/minute.
15. The method of claim 9 , wherein the etch stop layer comprises silicon nitride.
16. A method or forcing a dielectric, comprising:
forming a fluorine containing film on a substrate having a top surface,
forming a hardmask layer on the lop surface of the fluorine containing film;
forming via openings in the fluorine containing film, wherein the via openings define sidewalls; and
forming fluorine depleted sidewalls by exposing the hardmask layer and the sidewalls to a reducing plasma.
17. The method of claim 16 , further comprising exposing the hardmask layer and the sidewalls to the reducing plasma in a reaction chamber, wherein the reducing plasma is formed in a chamber remote from the reaction chamber containing the fluorine containing film.
18. The method of claim 16 , wherein the fluorine containing film comprises a material selected from the group consisting of a-C:F, parylene AF4, carbon-doped SiOF, fluorinated organic polymers, fluorinated silicone polymers, and SiOF.
19. The method of claim 16 , further comprising depositing a conductive material in the via openings.
20. The method of claim 16 , wherein the plasma is formed in a reaction chamber from ammonia and argon at a pressure between 1 mTorr and 50 Torr and an RF power of between 100 watts and 500 watts.
21. The method of claim 20 , wherein the ammonia is passed into the reaction chamber at a flow rate in the range of 10 sccm to 3 liters/minute.
22. A method of forming a dielectric, comprising:
forming a fluorine containing film on a substrate, the fluorine containing film having a top surface and sidewalls:
placing the substrate into a reaction chamber;
forming a fluorine depleted top surface and fluorine depleted sidewalls by simultaneously exposing the top surface and sidewalls of the fluorine containing film to a reducing plasma, wherein the reducing plasma is formed in a chamber remote from the reaction chamber containing the substrate;
forming a layer of a conductive material over the fluorine depleted sidewalls; and
forming an etch stop layer over the fluorine depleted top surface.
23. The method of claim 22 , wherein the substrate is a silicon wafer, and the fluorine containing film is a substantially planar insulating layer.
24. The method of claim 22 , wherein the plasma is formed from a hydrogen bearing precursor gas and a carrier gas.
25. The method of claim 24 , wherein the hydrogen bearing precursor comprises NH 3 gas.
26. The method of claim 25 , wherein the carrier gas comprises a gas selected from the group consisting of N 2 , Ar and He.
27. The method of claim 26 , wherein the fluorine containing film comprises a material selected from the group consisting of a-C:F, parylene AF4, carbon-doped SiOF, fluorinated organic polymers, fluorinated siloxane polymers, and SiOF.
28. The method of claim 22 , wherein the fluorine containing film comprises parylene-AF4.
29. The method of claim 28 , wherein the etch stop layer comprises silicon nitride.
30. The method of claim 22 , wherein the etch stop layer comprises silicon nitride.
31. A method of forming an inter layer dielectric in an integrated circuit, comprising:
depositing a fluorinated material on a substrate, the fluorinated material having a top surface;
forming via openings in the fluorinated material, wherein the via openings define sidewalls;
forming a fluorine depleted top surface and fluorine depleted sidewalls by simultaneously exposing the top surface and the sidewalls of the fluorinated material to a hydrogen containing plasma in a reaction chamber, wherein the plasma is formed in a chamber remote from the reaction chamber containing the fluorinated material;
forming a layer of a conductive material over the fluorine depleted sidewalls; and
forming an etch stop layer over the fluorine depleted top surface.
32. The method of claim 31 , wherein the fluorinated material is selected from the group consisting of a-C:F, parylene AF4, carbon-doped SiOF, fluorinated organic polymers, fluorinated siloxane polymers and SiOF.
33. The method of claim 32 , further comprising depositing a conductive material in the via openings.
34. The method of claim 32 , wherein the fluorinated material comprises parylene-AF4.
35. The method of claim 32 , wherein the plasma is formed in a reaction chamber from ammonia and argon at a pressure between 1 mTorr and 50 Torr and an RF power of between 100 watts and 500 watts.
36. The method of claim 35 , wherein the ammonia is passed into the reaction chamber at a flow rate in the range of 10 sccm to 3 liters/minute.