Timing analysis apparatus, systems, and methods
View Patent ↗An apparatus and a system, as well as a method and article, may operate to include receiving initial static timing environment data associated with a circuit at a graphical user interface, and generating a data file including a plural of all possible sources of a generated clock included in the circuit.
1. A method, comprising:
receiving initial static timing environment data associated with a circuit; and
generating a data file including a plurality of all possible sources of a generated clock included in the circuit.
2. The method of claim 1 , further comprising:
determining a selected mode of operation for the circuit; and
selecting a single source from the plurality of all possible sources as a true source of the generated clock associated with the selected mode of operation for the circuit.
3. The method of claim 2 , further comprising:
associating the selected mode of operation with a set of case analysis statements.
4. The method of claim 3 , further comprising:
applying the set of case analysis statements to an input port of a block.
5. The method of claim 1 , further comprising:
defining the plurality of all possible sources and the generated clock.
6. The method of claim 1 , wherein receiving the initial static timing environment data associated with the circuit includes defining an input clock to the circuit, further comprising:
defining a different input clock to the circuit; and
regenerating the data file including a different plurality of all possible sources of the generated clock included in the circuit.
7. The method of claim 1 , wherein generating the data file including the plurality of all possible sources of the generated clock included in the circuit further includes:
accessing a design constraint file associated with a netlist file for the circuit.
8. The method of claim 7 , further comprising:
selecting a set of interface constraints from the design constraint file for application to block timing.
9. The method of claim 1 , wherein the initial static timing environment data is selected from at least one of a design software version, a verification software version, a library type, an analysis type, a project designator, a netlist format, a netlist file path, a netlist stage, a link library, a database location, a customization option, and a design constraint selection.
10. The method of claim 9 , wherein the design constraint selection includes at least one of a clock constraint file, a general constraints file, a persistent constraints file, a parasitic constraints file, an operating conditions constraints file, an extraction file, and an exceptions file.
11. The method of claim 1 , further comprising:
creating a timing analysis script file.
12. The method of claim 1 , further comprising:
repeating receiving the initial static timing environment data and generating the data file for a number of blocks included in a chip, wherein at least one of the number of blocks is associated with a set of constraints; and
conducting a static timing analysis of the chip using the set of constraints.
13. An article comprising a machine-accessible medium having associated data, wherein the data, when accessed, results in a machine performing:
receiving initial static timing environment data associated with a circuit; and
generating a data file including a plurality of all possible sources of a generated clock included in the circuit.
14. The article of claim 13 , wherein the data, when accessed, results in the machine performing:
accessing a clock edge definition file.
15. The article of claim 13 , wherein generating the data file including the plurality of all possible sources of the generated clock included in the circuit further comprises:
creating a script file as an input to a timing analysis program.
16. The article of claim 13 , wherein the data, when accessed, results in the machine performing:
receiving a block-specific constraint including at least one of a case analysis, a false path, a multi-cycle path, and a disable timing information associated with a selected operational mode.
17. The article of claim 13 , wherein the data, when accessed, results in the machine performing:
repeating receiving the initial static timing environment data and generating the data file for a number of blocks included in a chip, wherein at least one of the number of blocks is associated with a set of constraints; and
storing the set of constraints for use in conducting a static timing analysis of the chip.
18. An apparatus, comprising:
a module to receive initial static timing environment data associated with a circuit; and
a module to generate a data file including a plurality of all possible sources of a generated clock included in the circuit.
19. The apparatus of claim 18 , further comprising:
a module to receive a block-specific constraint to be transmitted to the module to receive initial static timing environment data.
20. The apparatus of claim 18 , wherein the block-specific constraint includes at least one of a case analysis, a false path, a multi-cycle path, and a disable timing information associated with a selected operational mode.
21. The apparatus of claim 18 , further comprising:
a module to create the generated clock for each one of a plurality of valid modes of operation.
22. The apparatus of claim 18 , further comprising:
a module to detect a cross-clock domain timing path.
23. The apparatus of claim 18 , further comprising:
a module to receive an identification of a minimum number of nodes for case analysis.
24. A system, comprising:
a module to receive initial static timing environment data associated with a circuit at a graphical user interface;
a module to generate a data file including a plurality of all possible sources of a generated clock included in the circuit; and
a display to display the graphical user interface and a result of a timing analysis associated with the circuit.
25. The system of claim 24 , further comprising:
a module to receive a set of timing constraints included in the initial static timing environment.
26. The system of claim 24 , further comprising:
a module to receive a set of constraints from a prior initial static timing environment.
27. The system of claim 24 , further comprising:
a module to determine a set of all relationships between a set of all source clocks and a set of all generated clocks for the circuit.