Look-ahead carry adder circuit
View Patent ↗A look-ahead carry adder circuit has multiple stages that are grouped into a carry generation blocks. The size of one of the carry generation blocks is three stages. There may be other carry generation blocks that are of a size that is a whole number multiple of three stages. In an embodiment, the look-ahead carry adder has only one critical path. In a further embodiment, the load on the critical path is minimized by using buffers.
1. A method of adding two multi-bit addends, the method comprising:
receiving two multi-bit addends;
determining a propagate value and a corresponding generate value for each bit of the addends;
determining a carry-out value for each propagate value based at least in part on the propagate value and corresponding generate value, wherein the carry-out values are determined by a plurality of carry generation blocks, and wherein one of the carry generation blocks determines exactly three of the carry-out values, wherein determining every third carry-out value in said one of the carry generation blocks includes determining a group propagate value and a group generate value; and
determining a sum value for each carry-out value based at least in part on the carry-out value.
2. The method of claim 1 , wherein another of the carry generation blocks determines exactly six of the carry-out values.
3. The method of claim 1 , wherein the method further comprises determining an intermediate XOR value for each of said propagate values based on the propagate value and corresponding generate value, wherein sum values are based at least in part on the intermediate XOR values, and wherein intermediate XOR values are determined without using an XOR gate.
4. The method of claim 1 , wherein there is a single critical path through the plurality of carry generation blocks.
5. The method of claim 4 , wherein gates in the critical path have tapered transistor stacks.
6. The method of claim 1 , wherein determining one or more of the carry-out values includes combining a propagate value, a generate value, and a carry-in value in a gate that has only two transistor stacks.
7. A look-ahead carry adder circuit, comprising:
inputs to receive two multi-bit addends;
a plurality of blocks each of which is connected to one input bit of both of the multi-bit addends, wherein each block has a propagate output and a corresponding generate output;
a plurality of carry generation blocks each having inputs connected to two or more of said propagate outputs and two or more of said corresponding generate outputs, wherein one of the carry generation blocks is connected to exactly three of the propagate outputs and three of the corresponding generate outputs, and wherein each of the carry generation blocks has a plurality of carry outputs, each of said carry outputs to be determined based at least in part on one of the propagate values and one of the corresponding generate values, wherein in said one of the carry generation blocks, every third carry-out value is to be determined from a group propagate value and a group generate value; and
a plurality of final blocks each of which is connected to one of said carry outputs and each having a sum output.
8. The look-ahead carry adder circuit of claim 7 , wherein another of the carry generation blocks is connected to exactly six of the propagate outputs and six of the generate outputs.
9. The look-ahead carry adder circuit of claim 7 , wherein there is one critical path through the look-ahead carry adder circuit.
10. The look-ahead carry adder circuit of claim 9 , wherein the critical path includes an AND-OR-INVERT gate having an output connected to an input of an INVERT-AND-OR gate.
11. The look-ahead carry adder circuit of claim 10 , wherein the AND-OR-INVERT gate has only two transistor stacks.
12. The look-ahead carry adder circuit of claim 9 , wherein inputs and outputs of gates on the critical path are buffered to reduce the load on the critical path.
13. The look-ahead carry adder circuit of claim 7 , wherein the circuit contains a plurality of tapered transistor stacks.
14. The look-ahead carry adder circuit of claim 7 , wherein some of the carry generation blocks have a plurality of NAND gates that have a pair of inputs that are connected to one of the propagate outputs and one of the generate outputs through one or more buffers, and wherein each of the NAND gates is connected to an XOR output of a carry generation block through a buffer.
15. The look-ahead carry adder circuit of claim 7 , wherein the circuit has a plurality of gates to provide a group generate value and a plurality of gates to provide a group propagate value, and wherein group generate gates are arranged in clusters having a size that is a multiple of three.
16. A method of adding two multi-bit addends, the method comprising:
receiving two multi-bit addends;
determining a propagate value and a corresponding generate value for each bit of the addends;
determining a carry-out value for each propagate value based at least in part on the propagate value and corresponding generate value, wherein the carry-out values are determined by a plurality of carry generation blocks that include a plurality of tapered transistor stacks wherein in each stack, a transistor at a bottom of each stack is larger than a transistor at a top of each stack; and
determining a sum value for each carry-out value based at least on part of the carry-out value.
17. The method of claim 16 , wherein the method further comprises determining an intermediate XOR value for each of said propagate values based on the propagate value and corresponding generate value, wherein sum values are based at least in part on the intermediate XOR values, and wherein intermediate XOR values are determined without using an XOR gate.
18. The method of claim 16 , wherein there is a single critical path through the plurality of carry generation blocks.
19. The method of claim 18 , wherein gates in the critical path have tapered transistor stacks.
20. The method of claim 16 , wherein determining one or more of the carry-out values includes combining a propagate value, a generate value, and a carry-in value in a gate that has only two transistor stacks.
21. A look-ahead carry adder circuit, comprising:
inputs to receive two multi-bit addends;
a plurality of blocks each of which is connected to one input bit of both of the multi-bit addends, wherein each block has a propagate output and a generate output;
a plurality of carry generation blocks each having inputs connected to two or more of said propagate outputs and two or more of said generate outputs, wherein each of the carry generation blocks has a plurality of carry outputs, and wherein there is one critical path through the plurality of carry generation blocks wherein inputs and outputs of gates on the critical path are buffered to reduce the load on the critical path; and
a plurality of final blocks each of which is connected to one of said carry outputs and each having a sum output.
22. The look-ahead carry adder circuit of claim 21 , wherein the critical path includes an AND-OR-INVERT gate having an output connected to an input of an INVERT-AND-OR gate.
23. The look-ahead carry adder circuit of claim 22 , wherein the AND-OR-INVERT gate has only two transistor stacks.
24. The look-ahead carry adder circuit of claim 21 , wherein the circuit contains a plurality of tapered transistor stacks.
25. The look-ahead carry adder circuit of claim 21 , wherein some of the carry generation blocks have a plurality of NAND gates that have a pair of inputs that are connected to one of the propagate outputs and one of the generate outputs through one or more buffers, and wherein each of the NAND gates is connected to an XOR output of a carry generation block through a buffer.