IP Library Granted Patent US 7,304,373
Granted Patent B2
US 7,304,373 · App. 10/977,908 · Granted Dec 4, 2007

Power distribution within a folded flex package method and apparatus

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Quick Facts
Patent No.
US 7,304,373
App. No.
10/977,908
Granted
Dec 4, 2007
Kind
B2
Abstract

A device includes a folded flex substrate. A memory die is connected to a first side of the folded flex substrate. A logic die is connected to a second side of the folded flex substrate. A trace routing pattern of source voltage signals is identical to a trace routing pattern of collector voltage signals.

Claims (37)

1. An apparatus comprising:

a folded flex substrate having a first portion and a second portion, the first portion disposed on one side of a fold region, the second portion being disposed on another side of the fold region;

at least two source voltage junction boxes coupled to the folded flex substrate, the source voltage junction boxes are routed together through a first plurality of conductors;

at least two collector voltage junction boxes coupled to the folded flex substrate, the collector voltage junction boxes are routed together through a second plurality of conductors,

wherein the at least two source voltage junction boxes are oppositely disposed on different sides of the fold region, and the at least two collector voltage junction boxes are oppositely disposed on different sides of the fold region.

2. The apparatus of claim 1 , wherein a trace routing pattern of the at least two source voltage junction boxes is identical to a trace routing pattern of the at least two collector voltage junction boxes.

3. The apparatus of claim 1 , the folded flex substrate comprising a plurality of thin polyimide layers.

4. The apparatus of claim 1 , wherein bundled pairs of source voltage signals and bundled pairs of collector voltage signals to deliver uninterrupted power across the fold region.

5. A system comprising:

a memory device;

a power supply coupled to the memory device;

a device, the device coupled to the power supply and the memory device, the device including a processing device having a folded flex substrate, the folded flex substrate including:

a first portion and a second portion, the first portion and the second portion separated by a fold region;

a pair of source voltage junction boxes routed together through a first plurality of conductors, and

a pair of collector voltage junction boxes routed together through a second plurality of conductors.

6. The system of claim 5 , the device including a logic device.

7. The system of claim 5 , the processing device including a logic die coupled to the folded flex substrate, and

a memory die coupled to the logic die.

8. The system of claim 5 , wherein each source voltage junction box of the pair of source voltage junction boxes are oppositely disposed across the fold region, and each collector voltage junction box of the pair of collector voltage junction boxes are oppositely disposed across the fold region.

9. The system of claim 5 , wherein a trace routing pattern of the pair of source voltage junction boxes is identical to a trace routing pattern of the pair of collector voltage junction boxes.

10. The system of claim 5 , the folded flex substrate further including a plurality of thin polyimide layers.

11. The system of claim 5 , wherein bundled pairs of source voltage signals and bundled pairs of collector voltage signals to deliver uninterrupted power across the fold region.

12. An apparatus comprising:

a folded flex substrate;

a memory die coupled to a first side of the folded flex substrate;

a logic die coupled to a second side of the folded flex substrate;

a first source voltage junction box coupled to a first portion outside of a fold region of the folded flex substrate; and

a first collector voltage junction box coupled to the first portion outside of the fold region,

wherein a trace routing pattern of source voltage signals is identical to a trace routing pattern of collector voltage signals.

13. The apparatus of claim 12 , further comprising:

a second source voltage junction box coupled to a second portion outside of the fold region; and

a second collector voltage junction box coupled to the second portion outside of the fold region.

14. The apparatus of claim 13 , wherein the first source voltage junction box and the second source voltage junction box are routed together through a first plurality of vias.

15. The apparatus of claim 13 , wherein the first collector voltage junction box and the second collector voltage junction box are routed together through a second plurality of vias.

16. The apparatus of claim 15 , wherein the first side and the second side of the folded flex substrate are outside of the fold region.

17. The apparatus of claim 12 , the folded flex substrate comprising a plurality of thin polyimide layers.

18. The apparatus of claim 12 , wherein a plurality of bundled pairs of source voltage signals and a plurality of bundled pairs of collector voltage signals to deliver uninterrupted power across the fold region.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 4, 2013
From: INTEL CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030747/0001 →