Voltage controlled oscillator (VCO) tuning
View Patent ↗In accordance with certain described implementations, a voltage controlled oscillator (VCO) includes a VCO coarse tuning bank having multiple coarse tuning bank bits. Each coarse tuning bank bit has an associated bit capacitance. The bit capacitances of the coarse tuning bank bits may be selectively engaged using, for example, a single switching transistor for each coarse tuning bank bit.
1. A device comprising:
a voltage controlled oscillator (VCO) having an inductive-capacitive (LC) tank, the VCO capable of activating and deactivating respective capacitor pairs of the LC tank with respective single switching transistors;
wherein the VCO includes at least one VCO coarse tuning bank bit for a course tuning bank, the VCO coarse tuning bank bit comprising:
a pair of capacitors including a first capacitor and a second capacitor; the first capacitor coupled to a first node, and the second capacitor coupled to a second node;
a pair of bias transistors including a first bias transistor and a second bias transistor; the first bias transistor coupled between the first node and a third node, the second bias transistor coupled between the second node and the third node;
a switching transistor coupled between the first node and the second node, the switching transistor including a gate terminal that receives a coarse tuning bank bit input signal; and
an inverter that receives the coarse tuning bank bit input signal and produces an inverse coarse tuning bank bit input signal, the inverter to provide the inverse coarse tuning bank bit input signal to the third node.
2. The device as recited in claim 1 , wherein the VCO is adapted to generate a frequency responsive to the activated and deactivated capacitor pairs of the LC tank.
3. The device as recited in claim 2 , further comprising:
a transceiver that is adapted to accept the frequency from the VCO;
wherein the device comprises a mobile phone.
4. The device as recited in claim 2 , further comprising:
a central processing unit (CPU) that is adapted to accept the frequency from the VCO;
wherein the device comprises a computer.
5. The device as recited in claim 1 , wherein the coarse tuning bank includes multiple coarse tuning bit inputs that enable (i) collective activation and deactivation of the capacitor pairs and (ii) a coarse tuning of a frequency generated by the VCO.
6. The device as recited in claim 5 , wherein the VCO comprises a VCO core that includes a fine tuning input, the fine tuning input enabling a fine tuning of the frequency generated by the VCO.
7. The device as recited in claim 1 , wherein a parasitic capacitance of the pair of bias transistors can be reduced by providing the inverse coarse tuning bank bit input signal to the third node.
8. An integrated circuit (IC) comprising:
a voltage controlled oscillator (VCO) core having a first coarse tuning bank node and a second coarse tuning bank node, the VCO core including a core capacitance; and
a VCO coarse tuning bank that interfaces with the VCO core at the first coarse tuning bank node and the second coarse tuning bank node; the VCO coarse tuning bank including multiple coarse tuning bank bits, each coarse tuning bank bit comprising a pair of capacitors that are arranged in a differential structure, each pair of capacitors having a bit capacitance that is capable of being selectively engaged so as to contribute the bit capacitance to the core capacitance of the VCO core;
wherein each coarse tuning bank bit comprises a switching transistor that is capable of creating a common node between each pair of capacitors when the switching transistor is activated;
wherein the differential structure of each coarse tuning bank bit includes a pair of bias transistors, each respective bias transistor of the pair of bias transistors connected in series with a respective capacitor of the pair of capacitors; and
wherein each coarse tuning bank bit further comprises an inverter, the inverter to accept a coarse tuning bank bit signal input and to produce an inverted coarse tuning bank bit signal at a node to which the pair of bias transistors is coupled.
9. The IC as recited in claim 8 , wherein a first capacitor of each pair of capacitors is coupled to the first coarse tuning bank node, and a second capacitor of each pair of capacitors is coupled to the second coarse tuning bank node.
10. The IC as recited in claim 8 , wherein the VCO core and the VCO coarse tuning bank comprise a VCO having a total VCO capacitance, the total VCO capacitance established by the core capacitance and the bit capacitances of the multiple coarse tuning bank bits that have been selectively engaged.
11. A system comprising:
a signal source; and
a circuit comprising:
a first capacitor coupled to a first node;
a second capacitor coupled to a second node;
a first bias transistor coupled to the first node;
a second bias transistor coupled to the second node; and
a switching transistor coupled between the first node and the second node, the switching transistor including a gate terminal that receives a coarse tuning bank bit input signal at a third node;
wherein the first bias transistor is coupled between the first node and a fourth node, and the second bias transistor is coupled between the second node and the fourth node; and
wherein the circuit further comprises:
an inverter coupled between the third node and the fourth node; an input of the inverter corresponding to the third node, and an inverting output of the inverter corresponding to the fourth node.
12. The system as recited in claim 11 , wherein the first bias transistor includes a first gate terminal, and the second bias transistor includes a second gate terminal; and wherein the first gate terminal and the second gate terminal are connected to a supply voltage.
13. The system as recited in claim 11 , wherein the switching transistor comprises an N-channel metal oxide semiconductor (NMOS) transistor.
14. The system as recited in claim 11 , wherein a voltage at the first node drops below ground during operation of the circuit.
15. The system as recited in claim 11 , wherein the switching transistor shorts the first node and the second node when the switching transistor is activated by the coarse tuning bank bit input signal.
16. The system as recited in claim 11 , further comprising:
a voltage controlled oscillator (VCO) core having fifth node and a sixth node;
wherein the first capacitor is coupled between the first node and the fifth node, and the second capacitor is coupled between the second node and the sixth node.
17. The system as recited in claim 16 , wherein activation of the switching transistor by the coarse tuning bank bit input signal causes the first capacitor and the second capacitor to be engaged and to contribute a first capacitance and a second capacitance, respectively, to a core capacitance of the VCO core.
18. A method comprising:
applying a coarse tuning value to multiple coarse tuning bank inputs of multiple coarse tuning bank bits;
inverting the coarse tuning value to produce an inverse coarse tuning value;
selectively engaging coarse tuning bank bits of the multiple coarse tuning bank bits by selectively activating a single switch per capacitor pair of each coarse tuning bank bit responsive to the applied coarse tuning value; each respective coarse tuning bank bit including a respective bias transistor pair that is coupled to a respective capacitor pair, each bias transistor pair capable of producing a parasitic capacitance; and
applying the inverse coarse tuning value to each bias transistor pair so as to reduce the parasitic capacitance.
19. The method as recited in claim 18 , further comprising:
fine tuning a voltage controlled oscillator (VCO); and
operating the VCO in accordance with the fine tuning and the selectively engaged coarse tuning bank bits.
20. The method as recited in claim 19 , wherein the selectively engaging comprises:
causing capacitance of the capacitor pair to be contributed to an overall capacitance of the VCO for each coarse tuning bank bit that is engaged.
21. The method as recited in claim 18 , wherein the selectively engaging comprises:
shorting the capacitor pair, of which capacitors thereof are arranged in a differential relationship, for each coarse tuning bank bit that is engaged.
22. The method as recited in claim 21 , wherein the shorting comprises:
initiating a Miller effect with respect to at least one capacitor of the capacitor pair for each coarse tuning bank bit that is engaged.