Scalable traceback technique for channel decoder
View Patent ↗Apparatus, system, and method for scalable traceback techniques for channel decoding are described.
1. An apparatus, comprising:
a first input to receive a first portion of a state in a state register;
a second input to receive a second portion of said state in said state register;
a control unit to load said first portion of said current state to said first input, to load said second portion of said state to said second input, and to generate an output state corresponding to a vector stored at a memory address selected by said first portion of said state and then a portion of said vector selected by said second portion of said state;
a memory address generator coupled to said control unit; and
an offset generator coupled to said memory address generator, said offset generator is to receive an input corresponding a number of decoding states corresponding to said state register and to provide a bit mask output to select said memory address within a plurality of consecutive memory addresses and a memory stride to index a subsequent set of said plurality of memory addresses.
2. The apparatus of claim 1 , said memory address generator to receive said first portion of said state and to generate said memory address.
3. The apparatus of claim 2 , further comprising a multiplexer coupled to said memory address generator, said multiplexer to receive said second portion of said state to generate said output state.
4. The apparatus of claim 3 , further comprising a register to store input to said multiplexer, said register to store said vector.
5. A system, comprising:
an antenna; and
a device connected to said antenna, said device to include:
a first input to receive a first portion of a state in a state register;
a second input to receive a second portion of said state in said state register;
a control unit to load said first portion of said current state to said first input, to load said second portion of said state to said second input, and to generate an output state corresponding to a vector stored at a memory address selected by said first portion of said state and then a portion of said vector selected by said second portion of said state;
a memory address generator coupled to said control unit; and
an offset generator coupled to said memory address generator, said offset generator is to receive an input corresponding a number of decoding states corresponding to said state register and to provide a bit mask output to select said memory address within a plurality of consecutive memory addresses and a memory stride to index a subsequent set of said plurality of memory addresses.
6. The system of claim 5 , said memory address generator to receive said first portion of said state and to generate said memory address.
7. The system of claim 6 , wherein said device further comprises a multiplexer coupled to said memory address generator, said multiplexer to receive said second portion of said state to generate said output state.
8. The system of claim 7 , wherein said device further comprises a register to store input to said multiplexer, said register to store said vector.
9. A method, comprising:
receiving an input corresponding to a number of decoding states;
loading one of a plurality of sequentially stored traceback vectors comprising a plurality of bits from a traceback memory array stored in a traceback memory for a first of said states;
identifying a traceback bit among said plurality of bits of said loaded traceback vector;
providing a bit mask output to select a memory address within a plurality of consecutive memory addresses; and
creating a second state.
10. The method of claim 9 , wherein loading comprises loading a stored traceback vector comprising 2 K−1 bits, wherein 2 K−1 is a number of possible states.
11. The method of claim 9 , wherein identifying a traceback bit comprises using said first state as an index.
12. The method of claim 9 , wherein creating a second state comprises, creating a second state by inserting said traceback bit next to a most-significant bit position of said current state.
13. An article, comprising:
a storage medium;
said storage medium including stored instructions that, when executed by a processor, are operable to:
receive an input corresponding to a number of decoding states;
load one of a plurality of sequentially stored traceback vector comprising a plurality of bits from a traceback memory array stored in a traceback memory for a first state;
identify a traceback bit among said plurality of bits of said loaded traceback vector;
provide a bit mask output to select a memory address within a plurality of consecutive memory addresses; and
create a second state.
14. The article of claim 13 , wherein the stored instructions, when executed by a processor, are further operable to load a stored traceback vector comprising 2 K−1 bits, wherein 2 K−1 is a number of possible states.
15. The article of claim 13 , wherein the stored instructions, when executed by a processor, are further operable to identify a traceback bit using said first state as an index.
16. The article of claim 13 , wherein the stored instructions, when executed by a processor, are further operable to create a second state by inserting said traceback bit next to a most-significant bit position of said current state.