Granted Patent B2

US 7,161,908 · App. 10/256,475 · Granted Jan 9, 2007

Abstract

Claims (30)

1. An apparatus, comprising:

an input port to receive a stream of information packets;

an output port to transmit a stream of information packets; and

a throttling unit to insert a spare processing cycle in the transmitted stream of information packets, wherein the spare processing cycle is inserted after each pre-determined number of information packets;

a cycle per packet register to store a value indicating a number of processing cycles associated with each information packet;

a current cycle count register; and

a spare cycle count register.

2. The apparatus of claim 1 , wherein the spare processing cycle facilitates operation of a control unit.

3. The apparatus of claim 2 , wherein the operation of the control unit is associated with at least one of: (i) a bookkeeping task, (ii) a register set up task, (iii) a table set up task, (iv) a programming task, (v) an address insertion task, and (vi) a learning task.

4. The apparatus of claim 1 , wherein the input port receives the stream of information packets from an arbitration unit.

5. The apparatus of claim 4 , wherein the information packets in the received stream are associated with at least one media access control module.

6. The apparatus of claim 1 , wherein the stream of information packets is transmitted via a processing pipeline.

7. The apparatus of claim 1 , wherein said throttling unit is to:

initialize the current cycle count register;

increment the current cycle count register by the value stored in the cycles per packet register each time an information packet is processed; and

insert the spare processing cycle based on the values stored in the current cycle count register and the spare cycle count register.

8. The apparatus of claim 7 , wherein the spare processing cycle is inserted when the value in the current cycle count register is not less than the value in the spare cycle count register.

9. The apparatus of claim 1 , wherein said cycles per packet register and said spare cycle count register comprise control registers and said current cycle count register comprises an internal register.

10. The apparatus of claim 1 , wherein the apparatus is associated with at least one of: (i) a packet network, (ii) a local area network, (iii) an Ethernet network, (iv) a switch, and (v) a router.

11. The apparatus of claim 1 , wherein the apparatus is associated with an application specific integrated circuit.

12. A network device comprising:

a arbitration unit to receive information packet from a number of media access control modules; and

a throttling unit to receive a stream of information packets from the arbitration unit and to transmit a stream of information packets to a processing pipeline, wherein the throttling unit facilitates operation of a control unit,

wherein said throttling unit facilitates operation of the control unit by inserting spare processing cycles in the transmitted stream of information packets, wherein said throttling unit is further associated with:

a cycles per packet control register to store a value indicating a number of processing cycles required to transmit each information packet,

an internal current cycle count register, and

a spare cycle count control register, and said throttling unit is to:

initialize the internal current cycle count register;

increment the internal current cycle count register by the value stored in the cycles per packet control register each time an information packet is processed; and

insert the spare processing cycle based on the values stored in the internal current cycle count register and the spare cycle count control register.

Assignments (8)