Method, system, and apparatus for tracking defective cache lines
View Patent ↗To facilitate a processor during a reset operation, a linked list of pointers to a list of defective cache lines is created. The good data bits in defective cache lines are used for creating a linked list or other data structure for storing relevant information regarding defective cache lines.
1. An apparatus to store a plurality of pointers to a plurality of defective cache lines comprising:
an on-core resource to store a first pointer of the plurality of pointers to a first defective cache line of the plurality of defective cache lines; and
the plurality of defective cache lines, wherein each of the plurality of defective cache lines is to store a pointer to a next defective cache line of the plurality of defective cache lines.
2. The apparatus of claim 1 wherein the on-core resource on a processor is a machine specific register (MSR).
3. The apparatus of claim 1 wherein the plurality of defective cache lines are for a level three cache.
4. The apparatus of claim 1 wherein each of the defective cache lines has multiple copies of the pointer to a next disabled cache line of the plurality of disabled cache lines.
5. The apparatus of claim 1 wherein each of the defective cache lines has a single copy of the pointer and error correcting code, the pointer is for the next defective cache line of the plurality of defective cache lines.
6. The apparatus of claim 1 wherein a linked list of pointers to the plurality of defective cache lines is created to facilitate a processor during a reset operation.
7. The apparatus of claim 1 wherein a last defective cache line of the plurality of defective cache lines has a repeated termination pattern for the pointer to indicate that this is the last defective cache line.
8. The apparatus of claim 1 wherein a last defective cache line of the plurality of defective cache lines has an invalid way encoding for the pointer in the last defective cache line to indicate that this is the last defective cache line.
9. A method for disabling cache lines comprising:
searching an on-core resource for a first pointer to a first cache line;
disabling the first cache line if the first pointer exists in the on-core resource;
searching the first cache line for multiple copies of a second pointer to a second cache line;
determining whether the multiple copies of the second pointer are valid, if so, disabling the second cache line as indicated by the second pointer.
10. The method of claim 9 wherein disabling cache lines are performed during a warm reset of a processor.
11. The method of claim 9 wherein disabling cache lines places the cache lines in a disabled P state.
12. A method for disabling cache lines comprising:
searching an on-core resource for a first pointer to a first cache line;
disabling the first cache line if the first pointer exists in the on-core resource;
searching the first cache line for a second pointer to a second cache line;
disabling the second cache line if the second pointer exists in the first cache line; and
terminating the search if either an invalid way encoding or a repeated termination is detected.
13. The method of claim 12 wherein disabling cache lines are performed during a warm reset of a processor.
14. The method of claim 12 wherein disabling cache lines places the cache lines in a disabled P state.
15. An apparatus to store a plurality of pointers to a plurality of defective cache lines comprising:
an on-core resource to store a first pointer of the plurality of pointers to a first defective cache line of the plurality of defective cache lines; and
a plurality of defective cache lines with a plurality of good bits, the plurality of good bits in each of the plurality of defective cache lines to store a pointer to a next defective cache line of the plurality of defective cache lines.
16. The apparatus of claim 15 wherein the on-core resource on a processor is a machine specific register (MSR).
17. The apparatus of claim 15 wherein the plurality of defective cache lines are for a level three cache.
18. The apparatus of claim 15 wherein each of the defective cache lines has multiple copies of the pointer to a next defective cache line of the plurality of defective cache lines.
19. The apparatus of claim 15 wherein each of the defective cache lines has a single copy of the pointer and error correcting code, the pointer is for the next defective cache line of the plurality of defective cache lines.
20. The apparatus of claim 15 wherein a linked list of pointers to the plurality of defective cache lines is created to facilitate a processor during a reset operation.
21. The apparatus of claim 15 wherein a last defective cache line of the plurality of defective cache lines has a repeated termination pattern for the pointer to indicate that this is the last defective cache line.
22. The apparatus of claim 15 wherein a last defective cache line of the plurality of defective cache lines has an invalid way encoding for the pointer in the last defective cache line to indicate that this is the last defective cache line.
23. The apparatus of claim 15 wherein the on-core resource on a processor is an on chip RAM.
24. A system comprising:
at least one processor;
a cache, with a plurality of defective cache lines;
an on-core resource to store a first pointer of the plurality of pointers to a first defective cache line of the plurality of defective cache lines, the plurality of defective cache lines, wherein each of the plurality of defective cache lines is to store a pointer to a next defective cache line of the plurality of defective cache lines; and
the processor to utilize a linked list of the plurality of pointers to recreate and disable the plurality of defective cache lines during a reset operation.
25. The system of claim 24 wherein the reset operation is a warm reset.
26. The system of claim 24 wherein the cache with the plurality of defective cache lines is a level three cache.