IP Library Granted Patent US 7,145,481
Granted Patent B2
US 7,145,481 · App. 10/676,888 · Granted Dec 5, 2006

Method and apparatus for trusted keyboard scanning

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Quick Facts
Patent No.
US 7,145,481
App. No.
10/676,888
Granted
Dec 5, 2006
Kind
B2
Abstract

A keyboard scan engine integrated on a chipset to initiate a keyscan process. The keyboard scan engine detects a key depression. When in a trusted mode, the keyboard scan engine transmits a key code, corresponding to the key depression, through a trusted internal bus interface. When in a non-trusted mode, the keyboard scan engine transmits the key code through an interface to be processed by an onboard keyboard controller.

Claims (44)

1. A method comprising:

a keyboard scan engine integrated on a chipset initiating a keyscan process;

the keyboard scan engine detecting a key depression;

when in a trusted mode, transmitting a key code, corresponding to the key depression, through a trusted internal bus interface and transmitting the key code through a legacy interface when in a non-trusted mode.

2. The method of claim 1 , wherein the trusted internal bus interface is a trusted Universal Serial Bus (USB) interface.

3. The method of claim 1 , further including:

when in a non-trusted mode, sending a key code, corresponding to the key depression, through an interface to be processed by an onboard keyboard controller.

4. The method of claim 3 , wherein, in the not-trusted mode, the key code is transmitted to the onboard keyboard controller via a PS/2 interface.

5. The method of claim 1 , wherein the keyboard scan engine is integrated on an I/O hub controller of the chipset.

6. The method of claim 5 , wherein the I/O hub controller includes a port expander interfacing with a keyboard.

7. The method of claim 5 , wherein the keyboard scan engine implements a key scan algorithm.

8. A system comprising:

a central processing unit;

a memory unit; and

a keyboard scan engine integrated on a chipset, the keyboard scan engine to initiate a keyscan process, detect a key depression, and, when in a trusted mode, transmit a key code, corresponding to the key depression, through a trusted internal bus interface and transmitting the key code through a legacy interface when in a non-trusted mode.

9. The system of claim 8 , wherein the trusted internal bus interface is a trusted Universal Serial Bus (USB) interface.

10. The system of claim 8 , further including:

when in a non-trusted mode, the key code is to be transmitted through an interface to be processed by an onboard keyboard controller.

11. The system of claim 10 , wherein, in the not-trusted mode, the key code is to be transmitted to the onboard keyboard controller via a PS/2 interface.

12. The system of claim 8 , wherein the keyboard scan engine is integrated on an I/O hub controller of the chipset.

13. The system of claim 12 , wherein the I/O hub controller includes a port expander interfacing with a keyboard.

14. The system of claim 12 , wherein the keyboard scan engine implements a key scan algorithm.

15. A machine-readable medium having stored thereon a set of instructions, which when executed by a processor, perform a method comprising:

a keyboard scan engine integrated on a chipset initiating a keyscan process;

the keyboard scan engine detecting a key depression;

when in a trusted mode, transmitting a key code, corresponding to the key depression, through a trusted internal bus interface and transmitting the key code through a legacy interface when in a non-trusted mode.

16. The machine-readable medium of claim 15 , wherein the trusted internal bus interface is a trusted Universal Serial Bus (USB) interface.

17. The machine-readable medium of claim 15 , further including:

when in a non-trusted mode, sending a key code, corresponding to the key depression, through an interface to be processed by an onboard keyboard controller.

18. The machine-readable medium of claim 17 , wherein, in the not-trusted mode, the key code is transmitted to the onboard keyboard controller via a PS/2 interface.

19. The machine-readable medium of claim 15 , wherein the keyboard scan engine is integrated on an I/O hub controller of the chipset.

20. The machine-readable medium of claim 19 , wherein the I/O hub controller includes a port expander interfacing with a keyboard.

21. The machine-readable medium of claim 19 , wherein the keyboard scan engine implements a key scan algorithm.

22. A system comprising:

a central processing unit;

a memory unit;

a graphics controller; and

a keyboard scan engine integrated on a chipset, the keyboard scan engine to initiate a keyscan process, detect a key depression, and, when in a trusted mode, transmit a key code, corresponding to the key depression, through a trusted internal bus interface and transmitting the key code through a legacy interface when in a non-trusted mode.

23. The system of claim 22 , wherein the trusted internal bus interface is a trusted Universal Serial Bus (USB) interface.

24. The system of claim 22 , further including:

when in a non-trusted mode, the key code is to be transmitted through an interface to be processed by an onboard keyboard controller.

25. The system of claim 24 , wherein, in the not-trusted mode, the key code is to be transmitted to the onboard keyboard controller via a PS/2 interface.

26. The system of claim 22 , wherein the keyboard scan engine is integrated on I/O hub controller of the chipset.

27. The system of claim 26 , wherein the I/O hub controller includes a port expander interfacing with a keyboard.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 4, 2013
From: INTEL CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030747/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2004
From: COOPER, BARNES
To: INTEL CORPORATION
Reel/Frame 015009/0889 →