IP Library Granted Patent US 6,927,497
Granted Patent B2
US 6,927,497 · App. 10/226,070 · Granted Aug 9, 2005

Multi-die semiconductor package

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Quick Facts
Patent No.
US 6,927,497
App. No.
10/226,070
Granted
Aug 9, 2005
Kind
B2
Abstract

A semiconducting package includes a first capsule, a second capsule and an adhesive within a recess in a surface of the first capsule that secures the first capsule to the second capsule.

Claims (25)

1. A semiconducting package comprising:

a tape substrate that includes a front side and a back side;

a first capsule encapsulated onto the front side of the tape substrate, the first capsule including a surface having a recess;

a second capsule encapsulated onto the front side of the tape substrate, the tape substrate being folded to position the second capsule adjacent to the first capsule; and

an adhesive substantially filling the recess in the surface of the first capsule to secure the first capsule to the second capsule.

2. The semiconducting package of claim 1 , wherein the recess in the surface of the first capsule is a groove.

3. The semiconducting package of claim 1 , further comprising a third capsule encapsulated onto the front side of the tape substrate.

4. The semiconducting package of claim 3 , wherein the tape substrate is folded to position the third capsule against the back side of the tape substrate opposite to the second capsule.

5. The semiconducting package of claim 1 , wherein the recess in the surface of the first capsule includes a plurality of grooves.

6. The semiconducting package of claim 1 , wherein the second capsule includes a flat mating surface that engages the first capsule.

7. The semiconducting package of claim 1 , wherein the second capsule includes a surface having a recess such that the adhesive substantially fills the recess in the surface of the second capsule to secure the first capsule to the second capsule.

8. The semiconducting package of claim 7 , wherein the recess in the first capsule is at least partially aligned with the recess in the second capsule.

9. The semiconducting package of claim 1 , wherein the adhesive within the recess extends above the surface of the first capsule.

10. The semiconducting package of claim 1 , wherein the adhesive fills the recess in the surface of the first capsule such that the surface of the first capsule engages a flat mating surface of the second capsule.

11. A computer system comprising:

a bus;

a random access memory coupled to the bus;

a semiconducting package that is electrically connected to the bus, the semiconducting package including a first capsule and a second capsule that are each separately encapsulated onto a front side of a tape substrate, the tape substrate being folded to position the second capsule adjacent to the first capsule, the first capsule including a surface having a recess such that an adhesive substantially fills the recess to secure the first capsule to the second capsule.

12. The computer system of claim 11 , wherein the recess in the surface of the first capsule is a groove.

13. The semiconducting package of claim 11 , further comprising a third capsule encapsulated onto the front side of the tape substrate.

14. The semiconducting package of claim 13 , wherein the tape substrate is folded to position the third capsule against the back side of the tape substrate opposite to the second capsule.

15. The semiconducting package of claim 11 , wherein the second capsule includes a surface having a recess such that the adhesive substantially fills the recess in the surface of the second capsule to secure the first capsule to the second capsule.

16. The semiconducting package of claim 15 , wherein the recess in the first capsule is at least partially aligned with the recess in the second capsule.

17. The semiconducting package of claim 11 , wherein the adhesive within the recess extends above the surface of the first capsule.

18. The semiconducting package of claim 11 , wherein the adhesive fills the recess in the surface of the first capsule such that the surface of the first capsule engages a flat mating surface of the second capsule.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 4, 2013
From: INTEL CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030747/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2002
From: MEYERS, JOHN G.
To: INTEL CORPORATION
Reel/Frame 013241/0837 →