Controlling snoop activities using task table in multiprocessor system
View Patent ↗An embodiment of the present invention includes a task table to store a task entry corresponding to a first task associated with a first processor. A snoop controller controls snooping an access reference to a cache line in a task block in response to a second task cycle generated by a second processor according to a snoop condition.
1. An apparatus having a first processor comprising:
a task table to store a task entry corresponding to a first task associated with the first processor, the first task being a partitioned program routine having at least an instruction block; and
a snoop controller coupled to the task table to control snooping an access reference to a cache line in a task block in response to a second task cycle generated by a second processor according to a snoop condition, the second task cycle including a set of cache line accesses required by a second task.
2. The apparatus of claim 1 further comprising:
a table updater coupled to the task table to update the task entry based on a first task cycle generated by the first processor, the first task cycle including a set of cache line accesses required by the first task.
3. The apparatus of claim 2 wherein the task entry includes at least one of an entry task status, an entry task identifier (ID), an entry task address, an entry task block size, and an entry task terminator.
4. The apparatus of claim 3 wherein one of the first and second task cycles provides at least one of a cycle task ID, a task command, a memory request, a cycle task terminator, and a cycle task block size.
5. The apparatus of claim 4 wherein the task command includes at least one of an acquire task command, an evict task command, and an invalidate task command.
6. The apparatus of claim 5 wherein the entry task status is one of invalid and valid.
7. The apparatus of claim 6 wherein the snoop controller comprises:
a comparator to match the entry task ID and the cycle task ID; and
a snoop enable circuit to enable snooping the access reference when the entry task ID matches the cycle task ID and the entry task status is valid.
8. The apparatus of claim 7 wherein the first processor responds to a memory request according to a cache coherence protocol when snooping is enabled.
9. The apparatus of claim 7 wherein the snoop enable circuit disables snooping the access reference when a snooping disable condition occurs.
10. The apparatus of claim 9 wherein the snooping disable condition occurs when the entry table ID does not match the cycle task ID when the entry task status is invalid or when the task cycle terminator is reached.
11. A method comprising:
storing a task entry corresponding to a first task associated with a first processor in a task table, the first task being a partitioned program routine having at least an instruction block; and
controlling snooping an access reference to a cache line in a task block in response to a second task cycle generated by a second processor according to a snoop condition, the second task cycle including a set of cache line lines accesses required by a second task.
12. The method of claim 11 further comprising:
updating the task entry based on a first task cycle generated by the first processor, the first task cycle including a set of cache line accesses required by the first task.
13. The method of claim 12 wherein storing the task entry comprises storing at least one of an entry task status, an entry task identifier (ID), an entry task address, an entry task block size, and an entry task terminator.
14. The method of claim 13 further comprising providing at least one of a cycle task ID, a task command, a cycle task terminator, a memory request, and a cycle task block size in one of the first and second task cycles.
15. The method of claim 14 wherein providing the task command comprises providing at least one of an acquire task command, an evict task command, and an invalidate task command.
16. The method of claim 15 wherein storing the entry task status comprises storing the entry task status being one of invalid and valid.
17. The method of claim 16 wherein controlling snooping comprises:
matching the entry task ID and the cycle task ID; and
enabling snooping the access reference when the entry task ID matches the cycle task ID and the entry task status is valid.
18. The method of claim 17 further comprising responding to a memory request according to a cache coherence protocol when snooping is enabled.
19. The method of claim 17 wherein controlling snooping further comprises:
generating a snooping disable condition; and
disabling snooping the access reference when the snooping disable condition occurs.
20. The method of claim 19 wherein generating the snooping disable condition comprises:
generating the snooping disable condition when the entry table ID does not match the cycle task ID, when the entry task status is invalid, or when the task cycle terminator is reached.
21. An article of manufacture comprising:
a machine-accessible storage medium including data stored thereon that, when accessed by a machine, causes the machine to:
store a task entry corresponding to a first task associated with a first processor in a task table, the first task being a partitioned program routine having at least an instruction block; and
control snooping an access reference to a cache line in a task block in response to a second task cycle generated by a second processor according to a snoop condition, the second task cycle including a set of cache line accesses required by a second task.
22. The article of manufacture of claim 21 further comprising data that, when accessed, causes the machine to:
update the task entry based on a first task cycle generated by the first processor, the first task cycle including a set of cache line accesses required by the first task.
23. The article of manufacture of claim 22 wherein the data causing the machine to store the task entry comprises data that causes the machine to store at least one of an entry task status, an entry task identifier (ID), an entry task address, an entry task block size, and an entry task terminator.
24. The article of manufacture of claim 23 wherein the machine-accessible medium further comprises data, when accessed, causes the machine to provide at least one of a cycle task ID, a task command, a cycle task terminator, a memory request, and a cycle task block size in one of the first and second task cycles.
25. The article of manufacture of claim 24 wherein the data causing the machine to provide the task command comprises data that causes the machine to provide at least one of an acquire task command, an evict task command, and an invalidate task command.
26. The article of manufacture of claim 25 wherein the data causing the machine to store the entry task status comprises data that causes the machine to store the entry task status being one of invalid and valid.
27. The article of manufacture of claim 26 wherein the data causing the machine to control snooping comprises data that causes the machine to:
match the entry task ID and the cycle task ID; and
enable snooping the access reference when the entry task ID matches the cycle task ID and the entry task status is valid.
28. The article of manufacture of claim 27 further comprising data that, when accessed, causes the machine to respond to a memory request according to a cache coherence protocol when snooping is enabled.
29. The article of manufacture of claim 27 wherein the data causing the machine to control snooping further comprises data that causes the machine to:
generate a snooping disable condition; and
disable snooping the access reference when the snooping disable condition occurs.
30. The article of manufacture of claim 29 wherein the data causing the machine to generate the snooping disable condition comprises data that causes the machine to generate the snooping disable condition when the entry table ID does not match the cycle task ID, when the entry task status is invalid, or when the task cycle terminator is reached.
31. A system comprising:
a processor bus; and
at least first and second processors coupled to the processor bus, the first processor having a task manager and a cache memory, the task manager comprising:
a task table to store a task entry corresponding to a first task associated with the first processor, the first task being a partitioned program routine having at least an instruction block, and
a snoop controller coupled to the task table to control snooping an access reference to a cache line in a task block of the cache memory in response to a second task cycle generated by the second processor according to a snoop condition, the second task cycle including a set of cache line accesses required by a second task.
32. The system of claim 31 wherein the task manager further comprising:
a table updater coupled to the task table to update the task entry based on a first task cycle generated by the first processor, the first task cycle including a set of cache line accesses required by the first task.
33. The system of claim 32 wherein the task entry includes at least one of an entry task status, an entry task identifier (ID), an entry task address, an entry task block size, and an entry task terminator.
34. The system of claim 33 wherein one of the first and second task cycles provides at least one of a cycle task ID, a task command, a cycle task terminator, a memory request, and a cycle task block size.
35. The system of claim 34 wherein the task command includes at least one of an acquire task command, an evict task command, and an invalidate task command.
36. The system of claim 35 wherein the entry task status is one of invalid and valid.
37. The system of claim 36 wherein the snoop controller comprises:
a comparator to match the entry task ID and the cycle task ID; and
a snoop enable circuit to enable snooping the access reference when the entry task ID matches the cycle task ID and the entry task status is valid.
38. The system of claim 37 wherein the first processor responds to a memory request according to a cache coherence protocol when snooping is enabled.
39. The system of claim 37 wherein the snoop enable circuit disables snooping the access reference when a snooping disable condition occurs.
40. The system of claim 39 wherein the snooping disable condition occurs when the entry table ID does not match the cycle task ID, when the entry task status is invalid, or when the task cycle terminator is reached.