IP Library Granted Patent US 7,140,023
Granted Patent B2
US 7,140,023 · App. 10/699,638 · Granted Nov 21, 2006

Symbolic buffer allocation in local cache at a network processing element

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Quick Facts
Patent No.
US 7,140,023
App. No.
10/699,638
Granted
Nov 21, 2006
Kind
B2
Abstract

According to some embodiments, a portion of local memory allocated to a thread by a programming statement includes an indication of a read/write status of the portion and symbolically references a buffer name wherein the symbolically referenced buffer name includes both letters and numbers.

Claims (51)

1. A method, comprising:

retrieving a set of allocate buffer instructions from a storage device associated with a multithreaded network processing element, the network processing element having a local memory;

arranging for a first portion of the local memory to be allocated to a first thread context in accordance with an allocate buffer instruction that is associated with a first thread and symbolically references a buffer name, the allocate buffer instruction includes an indication of a read/write status of the first portion; and

arranging for a second portion of the local memory to be allocated to a second thread context in accordance with an allocate buffer instruction that is associated with a second thread and symbolically references the buffer name, the allocate buffer instruction includes an indication of a read/write status of the second portion; and

wherein the symbolically referenced buffer name includes both letters and numbers.

2. The method of claim 1 , further comprising:

including a base, size, and offset with the allocate buffer instruction associated with the first thread.

3. The method of claim 1 , wherein said arranging comprises translating the allocate buffer instructions into code.

4. The method of claim 1 , further comprising:

arranging for information associated with the first thread context to be stored in the first portion of the local memory; and

arranging for information associated with the second thread context to be stored in the second portion of the local memory.

5. The method of claim 1 , further comprising:

freeing the second portion of the local memory in accordance with another allocate buffer instruction that symbolically references the buffer name.

6. The method of claim 1 , wherein the symbolic reference to the buffer name may be passed in at least one of: (i) a function, and (ii) a macro.

7. The method of claim 1 , further comprising:

translating the set of allocate buffer instructions into code; and providing the code.

8. The method of claim 7 , wherein the provided code is associated with at least one of: (i) assembly language, and (ii) microcode.

9. The method of claim 1 , wherein the local memory comprises at least one of: (i) memory at the network processing element, (ii) hardware registers at the network processing element, and (iii) a local cache.

10. The method of claim 1 , wherein the network processing element is a reduced instruction set computer microengine in a network device.

11. The method of claim 10 , wherein the network device is associated with at least one of: (i) information packet header parsing, (ii) exception packet identification, (iii) information packet receipt, (iv) information packet transformation, and (v) information packet transmission.

12. The method of claim 10 , wherein the network device is associated with at least one of: (i) Internet protocol information packets, (ii) Ethernet information packets, (iii) asynchronous transfer mode protocol, (iv) a local area network, (v) a wide area network, (vi) a network processor, (vii) a switch, and (viii) a router.

13. An article, comprising:

a storage medium having stored thereon instructions that when executed by a machine result in the following:

retrieving a set of allocate buffer instructions from a storage device associated with a multithreaded network processing element, the network processing element having a local memory;

arranging for a first portion of the local memory to be allocated to a first thread context in accordance with a allocate buffer instruction that is associated with a first thread and symbolically references a buffer name, the allocate buffer instruction includes an indication of a read/write status of the first portion; and

arranging for a second portion of the local memory to be allocated to a second thread context in accordance with an allocate buffer instruction that is associated with a second thread and symbolically references the buffer name, the allocate buffer instruction includes an indication of a read/write status of the second portion; and

wherein the symbolically referenced buffer name includes both letters and numbers.

14. The article of claim 13 , wherein execution of the instructions further results in:

translating the set of allocate buffer instructions into code.

15. The article of claim 14 , wherein execution of the instructions further results in:

providing the code.

16. An article, comprising:

a processor; and

a medium storing a set of allocate buffer instructions , said allocate buffer instructions including:

an allocate buffer instruction associated with a first thread that includes an indication of a read/write status and uses a buffer name to symbolically reference information that a first thread context will store in local memory at a multithreaded network processing element; and

an allocate buffer instruction associated with a second thread that includes an indication of a read/write status and uses the buffer name to symbolically reference information that a second thread context will store in the local memory at the network processing element,

wherein the symbolically referenced buffer name includes both letters and numbers.

17. A method, comprising:

defining an allocate buffer instruction associated with a first thread that includes an indication of a read/write status and uses a buffer name to symbolically reference information that a first thread context will store in local memory at a multithreaded network processing element; and

defining allocate buffer instruction associated with a second thread that includes an indication of a read/write status and uses the buffer name to symbolically reference information that a second thread context will store in the local memory at the network processing element;

wherein the symbolically referenced buffer name includes both letters and numbers.

18. The method of claim 17 , further comprising:

arranging for the allocate buffer instruction to be translated into code.

19. A system, comprising:

a processor; and

a hard disk drive having stored therein instructions that when executed by a machine result in the following:

translating C programming language instructions into code, and

translating an additional allocate buffer instruction into code, the additional allocate buffer instruction including an indication of a read/write status and using a buffer name to symbolically reference information that a thread context will store in local memory at a multithreaded network processing element,

wherein the symbolically referenced buffer name includes both letters and numbers.

20. The system of claim 19 , further comprising:

an interface to facilitate a transfer of the code from the system to the network processing element.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 4, 2013
From: INTEL CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030747/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2004
From: TRAN, DENNIS D.; VIPAT, HARSHAWARDHAN; TONG, KHOI-NGUYEN T.; NAIK, UDAY R.
To: INTEL CORPORATION
Reel/Frame 015005/0265 →