Methods to perform cache coherency in multiprocessor system using reserve signals and control bits
View Patent ↗A cache controller prevents the use of data in a write-back cache memory from being propagated except to a client asserting a reserve signal, if a first control bit is set, or until the data is backed-up in a main memory, if a second control bit is set. The control bits inhibit portions of the cache memory from being accessed until the control bits are reset.
1. A method of providing cache coherency in a multiprocessor system, wherein the system comprises a core having at least one processor, a main memory, a cache controller, and at least one cache memory, and wherein the system further comprises at least one client, the method comprising:
the at least one client making an access request to the at least one cache memory, wherein the access request comprises a reserve signal and an address corresponding to a line in the at least one cache memory;
in response to the access request, the cache controller setting a no touch bit corresponding to the address in the at least one cache memory;
the cache controller setting a dirty bit corresponding to the no touch bit if the contents of the requested address are modified without modifying a corresponding location in the main memory;
in response to an access request by the at least one processor, determining if the no touch bit corresponding to the address is set and, if so, indicating a miss for the address in the cache memory;
in response to an access request by the at least one client, determining if the dirty bit corresponding to the address is set and,
if so, evicting the requested cache line to main memory, and resetting the dirty bit, and
if not, evicting the contents of the requested address in the cache memory to the client; and
resetting the no touch bit.
2. The method of claim 1 wherein the client comprises a direct memory access device not in the core.
3. The method of claim 1 , wherein the client comprises a processor not in the core.
4. The method of claim 1 , wherein the client comprises a processor in the core.