Method and process for determining a quotient

1. A method executed in a computing device for dividing by the integer number 48 to identify a number of fixed-length data cells, the method comprising:

receiving a first number representing a length of a data packet; and

using the first number in a combination of four additions and four bit-level shifts to produce a quotient representing a number of fixed-length data cells for storing contents of the data packet.

2. The method of claim 1 , wherein the four additions include adding one to the first number to produce a second number.

3. The method of claim 2 , wherein the four additions include adding the first number with the second number.

4. The method of claim 1 , wherein the four bit-level shifts include shifting a second number by a number of bits to the left.

5. The method of claim 4 , wherein the number of bits includes two bits.

6. A method executed in a computing device for dividing by the integer number 48 to identify a number of fixed-length data cells, the method comprising:

receiving a first number in a first register that represents a length of a data packet;

adding the first number with one to produce a second number in a second register;

left-shifting the second number by two bits to produce a third number in a third register;

adding the third number with the second number to produce a fourth number in a fourth register;

left-shifting the fourth number by four bits to produce a fifth number in a fifth register;

adding the fifth number with the fourth number to produce a sixth number in a sixth register;

left-shifting the sixth number by eight bits to produce a seventh number in a seventh register;

adding the seventh number with the sixth number to produce an eighth number in a eighth register; and

right-shifting the eighth number by twenty bits to produce a quotient that represents a number of fixed-length data cells for storing contents of the data packet.

7. The method of claim 6 , wherein the first through eighth registers are in the same computing device.

8. The method of claim 6 , wherein at least some of the first through eighth registers are in different computing devices.

9. The method of claim 6 , wherein the first through eighth registers are in a shared register stack accessible by different computing devices.

10. The method of claim 6 , wherein the first number includes a value between 0 and 65535.

11. The method of claim 6 , wherein the first number includes a sixteen bit binary number.

12. The method of claim 6 , wherein the quotient represents the number of fixed-length data cells capable of being transmitted on an asynchronous transfer mode (ATM) network.

13. A computer program product, tangibly embodied in an information carrier, for dividing by the integer number 48 to identify a number of fixed-length data cells, the computer program product being operable to cause a machine to:

receive a first number representing a length of a data packet; and

use the first number in a combination of four additions and four bit-level shifts to produce a quotient representing a number of fixed-length data cells for storing contents of the data packet.

14. The computer program product of claim 13 , wherein the four additions include adding one to the first number to produce a second number.

15. The computer program product of claim 14 , wherein the four additions include adding the first number with the second number.

16. The computer program product of claim 13 , wherein the four bit-level shifts include shifting a second number by a number of bits to the left.

17. The computer program product of claim 16 , wherein the number of bits includes two bits.

18. A computer program product, tangibly embodied in an information carrier, for dividing by the integer number 48 to identify a number of fixed-length data cells, the computer program product being operable to cause a machine to:

receive a first number representing a length of a data packet in a first register;

add the first number with one to produce a second number in a second register;

left-shift the second number by two bits to produce a third number in a third register;

add the third number with the second number to produce a fourth number in a fourth register;

left-shift the fourth number by four bits to produce a fifth number in a fifth register;

add the fifth number with the fourth number to produce a sixth number in a sixth register;

left-shift the sixth number by eight bits to produce a seventh number in a seventh register;

add the seventh number with the sixth number to produce an eighth number in an eighth register; and

right-shift the eighth number by twenty bits to produce a quotient representing a number of fixed-length data cells for storing contents of the data packet.

19. The computer program product of claim 18 , wherein the first through eighth registers are in the same computing device.

20. The computer program product of claim 18 , wherein at least some of the first through eighth registers are in different computing devices.

21. The computer program product of claim 18 , wherein the first through eighth registers are in a shared register stack accessible by different computing devices.

22. The computer program product of claim 18 , wherein the first number includes a value between 0 and 65535.

23. The computer program product of claim 18 , wherein the first number includes a sixteen bit binary number.

24. The computer program product of claim 18 , wherein the quotient represents the number of fixed-length data cells capable of being transmitted on an asynchronous transfer mode (ATM) network.

25. A division process residing in a computing device for dividing by the integer number 48 to identify a number of fixed-length data cells, comprising:

a receiving process to receive a first number representing a length of a data packet;

an adding process to use the first number in four additions; and

a shifting process to use the first number in four bit-level shifts to produce a quotient representing a number of fixed-length data cells for storing contents of the data packet.

26. The division process of claim 25 , wherein the four additions include adding one to the first number to produce a second number.

27. The division process of claim 26 , wherein the four additions include adding the first number with the second number.

28. The division process of claim 25 , wherein the four bit-level shifts include shifting a second number by a number of bits to the left.

29. The division process of claim 28 , wherein the number of bits includes two bits.

30. A division process residing in a computing device for dividing by the integer number 48 to identify a number of fixed-length data cells, comprising:

a receiving process to receive a first number representing a length of a data packet in a first register;

a first adding process to add the first number with one to produce a second number in a second register;

a first shifting process to left-shift the second number by two bits to produce a third number in a third register;

a second adding process to add the third number with the second number to produce a fourth number in a fourth register;

a second shifting process to left-shift the fourth number by four bits to produce a fifth number in a fifth register;

a third adding process to add the fifth number with the fourth number to produce a sixth number in a sixth register;

a third shifting process to left-shift the sixth number by eight bits to produce a seventh number in a seventh register;

a fourth adding process to add the seventh number with the sixth number to produce an eighth number in an eighth register; and

a fourth shifting process to right-shift the eighth number by twenty bits to produce a quotient representing a number of fixed-length data cells for storing contents of the data packet.

31. The division process of claim 30 , wherein the first through eighth registers are in the same computing device.

32. The division process of claim 30 , wherein at least some of the first through eighth registers are in different computing devices.

33. The division process of claim 30 , wherein the first through eighth registers are in a shared register stack accessible by different computing devices.

34. The division process of claim 30 , wherein the first number includes a value between 0 and 65535.

35. The division process of claim 30 , wherein the first number includes a sixteen bit binary number.

36. The division process of claim 30 , wherein the quotient represents the number of fixed-length data cells capable of being transmitted on an asynchronous transfer mode (ATM) network.

37. A system for dividing by the integer number 48 to identify a number of fixed-length data cells comprising:

a processor capable of receiving a first number representing a length of a data packet and using the first number in a combination of four additions and four bit-level shifts to produce a quotient representing a number of fixed-length data cells for storing contents of the data packet.

38. The system of claim 37 , wherein the four additions include adding one to the first number to produce a second number.

39. The system of claim 38 , wherein the four additions include adding the first number with the second number.

40. The system of claim 37 , wherein the four bit-level shifts include shifting a second number by a number of bits to the left.

41. A system comprising:

a router capable of receiving a first number representing a length of a data packet; and

a processor capable of using the first number in a combination of four additions and four bit-level shifts to produce a quotient representing a number of fixed-length data cells for storing contents of the data packet.

42. The system of claim 41 , wherein the four additions include adding one to the first number to produce a second number.

43. The system of claim 42 , wherein the four additions include adding the first number with the second number.

44. The system of claim 41 , wherein the four bit-level shifts include shifting a second number by a number of bits to the left.