Granted Patent B2

US 7,206,865 · App. 10/402,125 · Granted Apr 17, 2007

Abstract

Claims (85)

1. A method comprising:

detecting a write transaction request directed to a memory range mapped to an input/output (I/O) device;

intercepting the detected write transaction request if a transaction address associated with the detected write transaction falls within a predetermined write-combinable range of the memory range mapped to the I/O device;

storing data associated with the intercepted write transaction within a buffer assigned to the write-combinable range, the buffer having an associated, predetermined register and flushing data contents of the buffer to the I/O device if a write transaction is detected having a transaction address that is within a memory range mapped to the predetermined register and a transaction target that matches the predetermined register;

detecting a predetermined I/O port flush condition;

determining whether an initialization setting is set to override the detected flush condition; and

disregarding the detected I/O port flush condition if an override setting corresponding to the flush condition is detected.

2. The method of claim 1 , wherein flushing the data contents further comprising:

determining whether the transaction address identifies a memory range mapped to the predetermined register if the transaction address falls outside the write-combinable range;

identifying the buffer associated with the predetermined register if the transaction target matches the predetermined register;

flushing data contents of the identified buffer to the I/O device; and

forwarding the detected write transaction request to the predetermined register.

3. The method of claim 1 , wherein the method prior, to detecting the write transaction, further comprises:

receiving a first value indicating an address within a memory mapped I/O space assigned to the I/O device selected as a write-combining base address;

receiving a second value indicating a size of one or more write-combinable ranges within the memory mapped I/O space assigned to the I/O device;

receiving a third value indicating a number of write-combinable ranges to be formed within the memory mapped I/O space assigned to the I/O device;

receiving a fourth value indicating a size of a write-combining window to be formed within each of the one or more write-combinable ranges; and

assigning a respective buffer to the write-combining windows.

4. The method of claim 1 , wherein intercepting the detected write transaction further comprises:

identifying a target I/O port of the detected write transaction;

calculating one or more write-combinable ranges for the target I/O port according to a write-combining base address, a write-combinable range size and a count of the number of write-combinable ranges to be formed within the memory mapped I/O space assigned to the I/O device; and

comparing the transaction address with the one or more write-combinable ranges to determine whether the transaction address falls within one of the one or more write-combinable ranges.

5. The method of claim 1 , wherein storing the intercepted write transaction data further comprises:

identifying a write-combinable range corresponding to the transaction address;

determining whether a write-combining window assigned to the identified write-combinable range is open;

opening a write-combining window for an address range within the identified write-combinable range that corresponds to the transaction address if the assigned write-combining window is closed; and

storing data associated with the write transaction within a write-combining buffer assigned to the write combinable range.

6. The method of claim 5 further comprising:

determining whether an address of data contained within the assigned write-combining buffer corresponds to the transaction address if a write-combining window is open;

flushing the contents of the assigned write-combining buffer if a corresponding data address is detected; and

storing the transaction data within the assigned write-combining buffer after the assigned write-combining buffer is flushed.

7. The method of claim 5 , further comprising:

when a write-combining window is open, determining whether the open write-combining window corresponds to the transaction address; and

flushing the contents of the assigned write-combining buffer,

storing the transaction data within the assigned write-combining buffer,

closing the write-combining window, and

opening a write-combining window for an address range within the determined write-combinable range that corresponds to the transaction address if the write-combining window does not correspond to the transaction address.

8. The method of claim 1 further comprising:

detecting a predetermined I/O port flush condition;

identifying one or more write-combinable ranges of the I/O port having an open write-combining window;

identifying a buffer assigned to each open write-combining window; and

flushing data contained within the identified buffers to a corresponding I/O device.

9. The method of claim 1 , wherein the method, prior to detecting the write transaction, further comprises:

selecting an address within a memory mapped I/O space assigned to an I/O device as a write-combining base address;

selecting one or more write-combinable ranges within the assigned memory mapped I/O space;

determining a size of a write-combining window to be formed within each of the one or more write-combinable ranges;

assigning a respective I/O device register to each write-combinable range; and

updating one or more write-combining configuration registers according to the selected write-combining base address, the selected write-combinable ranges, the write-combining window size, and the assigned I/O device registers.

10. A method comprising:

selecting an address within a memory mapped I/O space assigned to an I/O device as a write-combining base address;

selecting one or more write-combinable ranges within the assigned memory mapped I/O space;

assigning a respective I/O device register to each write-combinable range; and

updating one or more write-combining configuration registers according to the selected write-combining base address, the selected write-combinable ranges, and the assigned I/O device registers.

11. The method of claim 10 , wherein updating the write-combining configuration registers further comprises:

determining one or more I/O port flushing conditions;

selecting one or more of the determined I/O port flush conditions to be overridden; and

updating one or more write-combining configuration settings to override the selected I/O port flush conditions.

12. The method of claim 10 , further comprising:

writing data to the selected I/O device within a selected write-combinable range; and

tracking data written to the write-combinable range to ensure compliance with one or more I/O ordering rules.

13. The method of claim 12 , wherein tracking data further comprises: identifying a write-combining buffer requiring flushing of its data contents, according to a corresponding I/O port data ordering nile; identifying an I/O device register assigned to the write-combining buffer and performing a write operation to the identified I/O device register to cause the flushing of the identified write-combining buffer.

14. The method of claim 10 , wherein determining the one or more write-combinable ranges further comprises:

selecting a write-combining window to be formed within each of the one or more write-combinable ranges;

selecting a size of each of the one or more write-combining windows; and

updating one or more of the write-combining configuration registers, according to the selected write-combining windows, and the selected size of the write-combining windows.

15. A computer readable storage medium including program instructions that direct a computer to function in a specified manner when executed by a processor, the program instructions comprising:

selecting an address within a memory mapped I/O space to an I/O device as a write-combining base address;

selecting one or more write-combinable ranges within the assigned memory mapped I/O space;

assigning a respective I/O device register to each selected write-combinable range; and

updating one or more write-combining configuration registers according to the selected write-combining base address, the selected write-combinable ranges, and the assigned I/O device registers.

16. The computer readable storage medium of claim 15 , wherein updating the chipset registers further comprises:

determining one or more I/O port flushing conditions;

selecting one or more of the determined I/O port flush conditions to be overridden; and

updating one or more write-combining configuration register settings to override the selected I/O port flush conditions.

17. The computer readable storage medium of claim 15 , further comprising:

writing data to the selected I/O device within a selected write-combinable range; and

tracking data written to the write-combinable range to ensure compliance with one or more I/O ordering rules.

18. The computer readable storage medium of claim 17 , wherein ensuring compliance further comprises:

identifying a write-combining buffer requiring flushing of its data contents, according to corresponding I/O port data ordering rule;

identifying an I/O device register assigned to the write-combining buffer; and

performing a write operation to the determined I/O device register to cause the flushing of the write-combining buffer.

19. The computer readable storage medium of claim 15 , wherein determining the one or more write-combining windows further comprises:

selecting a write-combining window to be formed within each of the one or more write-combinable ranges;

selecting a size of each of the one or more write-combining windows; and

updating one or more of the write-combining configuration registers according to the selected write-combining window, and the selected size of the write-combining windows.

Assignments (9)