Interconnect structure in integrated circuits
View Patent ↗A device includes an interconnect structure having a number of circuit paths to transfer signals. The circuit paths transfer the signals at different speed to reduce the coupling capacitance effect between adjacent circuit paths.
1. A device comprising:
a functional unit;
a plurality of circuit paths including a first circuit path and a second circuit path coupled to the functional unit; and
a plurality of additional circuit paths including a third circuit pat and a fourth circuit path coupled to the functional unit and interleaved with the plurality of circuit paths such that the third circuit path is between the first and second circuit paths and the second circuit path is between the third and fourth circuit paths, each of the first and second circuit paths including a number of first drive units, each of the first drive units including an input node, an output node, a first transistor and a second transistor coupled to the input and output nodes, the first transistor of each of the first drive units including a source region coupled to a first supply node and a body region coupled to a first bias node, the second transistor of each of the first drive units including a source region coupled to a second supply node and a body region coupled to a second bias node, wherein each of the third and fourth circuit paths includes a number of second drive units, each of the second drive units including third transistor and a fourth transistor, the third transistor of each of the second drive units including a source region coupled to the first supply node and a body region coupled to the first supply node, the fourth transistor of each of the second drive units including a source region coupled to the second supply node and a body region coupled to the second supply node.
2. The device of claim 1 , wherein the first and second circuit paths have an equal number of circuit elements.
3. The device of claim 2 , wherein the first and second transistors in each of the first drive units form an inverter.
4. The device of claim 3 further comprising at least one latch coupled between two of the first drive units.
5. The device of claim 1 , wherein the first transistor of each of the first drive units has a threshold voltage unequal to a threshold voltage of the third transistor of each of the second drive units, and wherein the second transistor of each of the first drive units has a threshold voltage unequal to a threshold voltage of the fourth transistor of each of the second drive units.
6. The device of claim 5 , wherein the first transistor of each of the first drive units and the third transistor of each of the second drive units have an equal transistor channel width and an equal transistor channel length, and wherein the second transistor of each of the first drive units and the fourth transistor of each of the second drive units have an equal transistor channel width and an equal transistor channel length.
7. The device of claim 6 , wherein each of the first and second circuit paths and each of the third and fourth circuit paths includes matched drive units.
8. A device comprising:
a functional unit;
a plurality of circuit paths including a first circuit path and a second circuit path coupled to the functional unit; and
a plurality of circuit paths including a third circuit path and a fourth circuit path coupled to the functional unit and interleaved with the plurality of circuit paths such that the third circuit path is between the first and second circuit paths and the second circuit path is between the third and fourth circuit paths, each of the first and second circuit paths including a number of drive units with a first drive unit having an output node coupled to an input node of a first additional drive unit, each of the third and fourth circuit paths including a number of drive units with a second drive unit and a second additional drive unit, the first drive unit including a first transistor having a source region coupled to a first supply node and a body region coupled to a first bias node, and a second transistor having a source region coupled to a second supply node and a body region coupled to the second supply node, the first additional drive unit including a first additional transistor having a source region coupled to the first supply node and a body region coupled to the first supply node, and a second transistor having a source region coupled to the second supply node and a body region coupled to a second bias node.
9. The device of claim 8 , wherein the second drive unit include an output node coupled to an input node of the second additional drive unit, the second drive unit including a first transistor having a source region coupled to the first supply node and a body region coupled to the first bias node, and a second transistor having a source region coupled to the second supply node and a body region coupled to the second supply node, the second additional drive unit including a first additional transistor having a source region coupled to the first supply node and a body region coupled to the first supply node, and a second transistor having a source region coupled to the second supply node and a body region coupled to a second bias node.
10. The device of claim 9 , wherein the number of drive units of each of the first and second circuit paths includes a further drive unit having an input node coupled to an output node of the first additional drive unit, the further unit drive including a first transistor having a source region coupled to the first supply node and a body region coupled to the first bias node, and a second transistor having a source region coupled to the second supply node and a body region coupled to the second supply node.
11. The device of claim 10 further comprising at least one latch coupled between two of the drive units of one of the first and second circuit paths, and at least one latch coupled between two of the drive units of one of the third and fourth circuit paths.
12. The device of claim 8 , wherein each of the first and second circuit paths and each of the third and fourth circuit paths include identical drive units.
13. The device of claim 8 , wherein each of the first and second circuit paths and each of the third and fourth circuit paths have an equal number of circuit elements.
14. A device comprising:
a functional unit;
a plurality of circuit paths including a first circuit path and a second circuit path coupled to the functional unit; and
a plurality of additional circuit paths including a third circuit path and a fourth circuit path coupled to the functional unit and interleaved with the plurality of circuit paths such that the third circuit path is between the first and second circuit paths and the second circuit path is between the third and fourth circuit paths, each of the first and second circuit paths including a number of drive units with a first drive unit having an output node coupled to an input node of a first additional drive unit, each of the third and fourth circuit paths including a number of drive units with a second drive unit and a second additional drive unit, the first drive unit including a first transistor of a first transistor type and a second transistor of a second transistor type, the first transistor having a threshold voltage lower than a threshold voltage the second transistor, the first additional drive unit including a third transistor of the first transistor type and a fourth transistor of the second transistor type, the third transistor having threshold voltage greater than a threshold voltage the fourth transistor.
15. The device of claim 14 , wherein the fourth transistor includes a source region coupled to a supply node and a body region coupled to a bias node.
16. The device of claim 14 , wherein the first transistor includes a source region coupled to a supply node and a body region coupled to a bias node.
17. The device of claim 16 , wherein the the number of drive units of each of the first and second circuit paths includes a further drive unit having an input node coupled to an output node of the first additional drive unit, the further unit drive including a fifth transistor of the first transistor type and a sixth transistor of the second transistor type, the fifth transistor having a threshold voltage lower than a threshold voltage the sixth transistor.
18. The device of claim 17 further comprising at least one latch coupled between two of the drive units of one of the first and second circuit paths, and at least one latch coupled between two of the drive units of one of the third and fourth circuit paths.
19. The device of claim 14 , wherein each of the first and second circuit paths and each of the third and fourth circuit paths include drive units having matched constructions.
20. The device of claim 19 , wherein each of the first and second circuit paths and each of the third and fourth circuit paths have an equal number of circuit elements.
21. A system comprising;
a first integrated circuit;
a second integrated circuit; and
an interconnect structure coupled between the first and second integrated circuits, the interconnect structure including:
a plurality of first circuit paths including a first circuit path and a second circuit path coupled to the functional unit; and
a plurality of additional circuit paths including a third circuit path and a fourth circuit path interleaved with the plurality of first circuit paths such that the third circuit path is between the first and second circuit paths and the second circuit path is between the third and fourth circuit paths, the first transistor of each of the first drive units including a source region coupled to a first supply node and a body region coupled to a first bias node, the second transistor of each of the first drive units including a source region coupled to a second supply node and a body region coupled to a second bias node, wherein each of the third and fourth circuit paths includes a number of second drive units, each of the second chive units including third transistor and a fourth transistor, the third transistor of each of the second drive units including a source region coupled to the first supply node and a body region coupled to the first supply node, the fourth transistor of each of the second drive units including a source region coupled to the second supply node and a body region coupled to the second supply node.
22. The system of claim 21 , wherein the first and second circuit paths have an equal number of circuit elements.
23. The system of claim 22 further comprising a number of first latches, and a number of second latches, wherein at least two of the first latches are coupled in one of the first and second circuit paths, and wherein at least two of the second latches are coupled in one of the third and fourth circuit paths.
24. The system of claim 21 , wherein the first transistor of each of the first drive units has a threshold voltage unequal to a threshold voltage of the third transistor of each of the second drive units, and wherein the second transistor of each of the first drive units has a threshold voltage unequal to a threshold voltage of the fourth transistor of each of the second drive units.
25. The system of claim 24 , wherein the first and second integrated circuits are formed in a single chip.