Structured, electrically-formed floating gate for flash memories
View Patent ↗Semiconductor memory devices and methods to fabricate thereof are described. A first gate base is formed on a first insulating layer on a substrate. A first gate fin is formed on the first gate base. The first gate fin has a top and sidewalls. Next, a second insulating layer is formed on the top and sidewalls of the first gate fin and portions of the first gate base. A second gate is formed on the second insulating layer. Source and drain regions are formed in the substrate at opposite sides of the first gate base. In one embodiment, the first gate fin includes an undoped polysilicon and the first gate base includes an n-type polysilicon. In another embodiment, the first gate fin includes an undoped amorphous silicon and the first gate base includes an n-type amorphous silicon.
1. A method, comprising:
forming a first gate electrode having a first gate electrode base on a first insulating layer on a substrate and a first gate electrode fin on the base, wherein the first gate electrode base includes an n-type doped silicon, and the first gate electrode fin includes an undoped silicon that remains undoped throughout the method and wherein the first gate electrode base is degenerately doped;
forming a second insulating layer on the first gate electrode covering a top and sidewalls of the fin and portions of the base; and
forming a second gate electrode on the second insulating layer.
2. The method of claim 1 , wherein the fin includes an undoped polysilicon and the base includes an n-type doped polysilicon.
3. The method of claim 1 , wherein the fin includes an undoped amorphous silicon and the base includes an n-type doped amorphous silicon.
4. The method of claim 1 , wherein the fin is formed by performing the operations comprising:
forming spacers over the base of the first gate electrode;
depositing a fin layer between the spacers;
etching back the fin layer; and
removing the spacers.
5. The method of claim 4 , wherein the forming the spacers includes
forming a nitride/oxide/first gate electrode base stack and
depositing a third insulating layer on the first insulating layer at opposite sides of the stack;
removing the nitride to expose the oxide; and
depositing a nitride layer on the oxide layer adjacent to the third insulating layer, and
etching back the nitride layer.
6. A method to fabricate a memory integrated circuit, comprising:
forming one or more first nitride/second oxide/ first gate base stacks on a first oxide layer on a substrate, wherein the first gate base includes an n-type doped silicon;
forming a third oxide layer on the first oxide adjacent to the one or more first nitride/second oxide/ floating gate base stacks;
removing the first nitride layer to expose the second oxide layer;
depositing a second nitride layer on the second oxide layer adjacent to the third oxide layer;
etching back the second nitride layer through a portion of the second oxide layer to form spacers over the first gate base;
depositing a fin layer that includes an undoped silicon that remains undoped throughout the method on the first gate base that is degenerately doped between the spacers to form a first gate electrode fin on the first gate base; and
etching back the fin layer to form one or more first gate fins on one or more first gate bases.
7. The method of claim 6 further comprising:
removing the spacers and the second oxide layer from the one or more first gate bases;
depositing a dielectric layer over the one or more first gate fins;
depositing a second gate layer over the dielectric layer;
patterning and etching the second gate layer to form one or more second gates.
8. The method of claim 6 , further comprising:
forming source and drain regions in the substrate, at opposite sides of each of the one or more first nitride/second oxide/ first gate base stacks.
9. The method of claim 6 , wherein the one or more first gate fins include an undoped polysilicon, and the one or more first gate bases include an n-type polysilicon.
10. The method of claim 6 , wherein the one or more first gate fins include an undoped amorphous silicon, and the one or more first gate bases include an n-type amorphous silicon.