Flash memory program and erase operations
View Patent ↗A flash memory device includes a charge pump having a capacity that is preset to a particular value. The flash memory device includes a measuring circuit to measure the actual capacity of the charge pump and to reset the capacity of the charge pump to a value based on the measured capacity.
1. An apparatus comprising:
a charge pump having a capacity that is preset to a particular value to simultaneously affect a first number of flash memory cells at a particular voltage; and
a measuring circuit including a voltage sensor to sense a voltage at an input and output of the charge pump and a temperature sensor to measure the temperature of the charge pump, wherein the measuring circuit is configured to measure an actual capacity of the charge pump and to reset the capacity of the charge pump to a second value based on the measure capacity to simultaneously affect a second number of flash memory cells.
2. The apparatus of claim 1 wherein an output of the charge pump is preset to operate at particular voltage and current levels.
3. The apparatus of claim 1 wherein the measuring circuit includes a current sensor to sense a current at an output of the charge pump.
4. An apparatus comprising:
an array of memory cells; and
a charge pump circuit coupled to the array of memory cells to drive the array of memory cells, the charge pump circuit comprising:
a charge pump having a capacity that is preset to a particular value to simultaneously affect a first number of flash memory cells at a particular voltage; and
a measuring circuit including a voltage sensor to sense a voltage at an input and output of the charge pump and a temperature sensor to measure the temperature of the charge pump, wherein the measuring circuit is configured to measure an actual capacity of the charge pump and to reset the capacity of the charge pump to a second value based on the measured capacity to simultaneously affect a second number of flash memory cells.
5. The apparatus of claim 4 wherein an output of the charge pump is preset to operate at particular voltage and current levels.
6. The apparatus of claim 4 wherein the measuring circuit includes a current sensor to sense a current at an output of the charge pump.
7. A computer system comprising:
a central processor; and
a memory coupled to the central processor, the memory comprising:
an array of memory cells, and
a charge pump circuit coupled to the array of memory cells to drive the array of memory cells, the charge pump circuit comprising:
a charge pump having a capacity that is preset to a particular value to simultaneously affect a first number of flash memory cells at a particular voltage, and
a measuring circuit including a voltage sensor to sense a voltage at an input and output of the charge pump and a temperature sensor to measure the temperature of the charge pump, wherein the measuring circuit is configured to measure an actual capacity of the charge pump and to reset the capacity of the charge pump to a second value based on the measured capacitity to simultaneously affect a second number of flash memory cells.
8. The computer system of claim 7 wherein an output of the charge pump is preset to operate at particular voltage and current levels.
9. The computer system of claim 7 wherein the measuring circuit includes a current sensor to sense the current at an input of the charge pump.
10. A method comprising:
establishing a nominal value for a capacity of a charge pump sufficient to simultaneously affect a first number of flash memory cells at a particular voltage;
characterizing an actual capacity of the charge pump by measuring an output voltage level of the charge pump while an output current of the charge pump is kept at a constant value; and
resetting the nominal capacity value of the charge pump to a second capacity value based on the actual capacity,
wherein the second capacity value of the charge pump is sufficient to simultaneously affect a second number of flash memory cells.
11. The method of claim 10 , wherein the second capacity value is reset by resetting the output value of the charge pump.
12. The method of claim 10 , wherein the second number of flash memory cells is greater than the first number of memory cells.
13. The method of claim 10 , wherein characterizing the charge pump includes a temperature sensor to measure the temperature of the charge pump.
14. A method comprising:
establishing a nominal value for a capacity of a charge pump sufficient to simultaneously affect a first number of flash memory cells at a particular current;
characterizing an actual capacity of the charge pump by measuring an output current level of the charge pump while an output voltage of the charge pump is kept at a constant value; and
resetting the nominal capacity value of the charge pump to a second capacity value based on the actual capacity,
wherein the second capacity value of the charge pump is sufficient to simultaneously affect a second number of flash memory cells.
15. The method of claim 14 , wherein the second capacity value is reset by resetting the output current level of the charge pump.
16. The method of claim 14 , wherein the second number of flash memory cells is greater than the first number of memory cells.
17. The method of claim 14 , wherein characterizing the charge pump includes a temperature sensor to measure the temperature of the charge pump.
18. The method of claim 14 , wherein affecting the flash memory cells comprises at least one of programming, erasing and reading the flash memory cells.
19. A method comprising:
recognizing a difference between a nominal capacity value of a charge pump sufficient to simultaneously affect a first number of flash memory cells and an actual capacity value sufficient to simultaneously affect a second number of flash memory cells;
resetting the nominal value to the actual capacity value; and
using the actual capacity value of the charge pump to simultaneously affect the second number of flash memory cells,
wherein the second number of flash memory cells is greater than the first number of flash memory cells.