IP Library Granted Patent US 7,124,412
Granted Patent B2
US 7,124,412 · App. 09/737,140 · Granted Oct 17, 2006

Extensible BIOS error log

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Quick Facts
Patent No.
US 7,124,412
App. No.
09/737,140
Granted
Oct 17, 2006
Kind
B2
Abstract

An apparatus that includes a BIOS routine, and a method executed during a BIOS routine, that includes a stored BIOS program causing a computer to receive information, including error information, from at least one first units coupled to the computer, store the information in a memory; and for each of at least one second units coupled to the computer, receive an initial request for the information from the second unit and in response to the request, provide to the second unit at least one of the information stored before the receipt of the request if any is stored, and provide to the second unit at least one of the information to the second unit received subsequent to the request.

Claims (46)

1. A method comprising:

a processor executing a BIOS routine by receiving information from at least a first computing system unit, the information comprising at least one of error information, status information, and configuration information;

the processor executing the BIOS routine by storing the received information in a memory;

for a second computing system unit,

the processor executing the BIOS routine by receiving an initial request from the second computing system unit for the received information;

the processor executing the BIOS routine by providing to the second computing system unit in response to the received request at least one of the received information stored in the memory before the receipt of the initial request if any is stored; and

the processor executing the BIOS routine by providing to the second computing system unit at least one of the received information received subsequent to the initial request;

wherein the provided received information stored before the receipt of the request includes one of all the received information and a categorized subset of all the received information.

2. The method defined in claim 1 wherein the information comprises at least one of unit information, system information, error information, status information, configuration information, and event information.

3. The method defined in claim 1 wherein the receiving the information from the first unit is according to an API.

4. The method defined in claim 1 wherein the providing the information to the second unit is according to an API.

5. The method defined in claim 1 wherein the storing the received information in a memory is according to a time of receipt of the information.

6. The method defined in claim 1 wherein the providing at least one of the received information stored in the memory before a receipt of the request is according to a time of receipt by the processor.

7. The method defined in claim 1 wherein the information received by the processor is appended to include at least one of a sequence number and an absolute time.

8. The method defined in claim 1 wherein the provided information received subsequent to the request includes one of all the received information and a categorized subset of all the received information.

9. A machine-readable medium that provides instructions, which when executed by a processor, cause said processor to perform operations comprising:

during execution of a BIOS routine, receiving information from at least one first computing system unit, the information comprising at least one of error information, status information, and configuration information;

during execution of the BIOS routine, storing the received information in a memory;

for a second computing system unit,

during execution of the BIOS routine, receiving an initial request for the received information from the second computing system unit;

during execution of the BIOS routine in response to the initial request, providing to the second computing system unit at least one of the information stored in the memory before the receipt of the initial request if any is stored; and

during execution of the BIOS routine, providing to the second computing system unit at least one of the received information received subsequent to the initial request;

wherein the provided received information stored before the receipt of the request includes one of all the received information and a categorized subset of all the received information.

10. The medium defined in claim 9 wherein the information comprises at least one of unit information, system information, error information, status information, configuration information, and event information.

11. The medium defined in claim 9 wherein the receiving information is according to an API.

12. The medium defined in claim 9 wherein the providing the information stored to the second units is according to an API.

13. The medium defined in claim 9 wherein the storing the received information in a memory is according to a time of receipt of the information.

14. The medium defined in claim 9 wherein the providing the received information stored in the memory before a receipt of the request is according to a time of receipt by the processor.

15. The medium defined in claim 9 wherein the information received is appended to include at least one of a sequence number and an absolute time.

16. The medium defined in claim 9 wherein the provided information received subsequent to the request includes one of all the received information and a categorized subset of all the received information.

17. A computer that comprises:

a stored BIOS program in a non-volatile memory that includes instructions that cause the computer to:

receive information from a first unit coupled to the computer, the information comprising at least one of error information, status information, and configuration information;

store the received information in a memory;

for a second unit coupled to the computer,

receive an initial request for the information from the second unit;

in response to the initial request, provide to the second unit at least one of the information stored in the memory before the receipt of the initial request if any is stored, and

provide to the second unit at least one of the received information to the second unit received subsequent to initial the request;

wherein the provided received information stored before the receipt of the request includes one of all the received information and a categorized subset of all the received information.

18. The computer defined in claim 17 where the information includes at least one of unit information, system information, error information, status information, configuration information, and event information.

19. The computer defined in claim 17 wherein the receive information from the first units is according to an API.

20. The computer defined in claim 17 wherein the provide to the second unit information is according to an API.

21. The computer defined in claim 17 wherein the store the received information in a memory is according to a time or receipt of the information.

22. The computer defined in claim 17 wherein the provide the received information stored in the memory before a receipt of the request is according to a time of receipt of the information.

23. The computer defined in claim 17 wherein the information received by the processor is appended to include at least one of a sequence number and an absolute time.

24. The computer defined in claim 17 wherein the provided information received subsequent to the request includes one of all the received information and a categorized subset of all the received information.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 4, 2013
From: INTEL CORPORATION
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030747/0001 →