A clock network comprises a clock distribution path coupled to a circuit. The clock distribution path and the circuit are formed on a substrate. The clock distribution path comprises a plurality of interconnected elements and one or more disconnected elements. The disconnected elements can be connected to the plurality of interconnected elements after the clock distribution path is tested in connection with the circuit. In one embodiment, the disconnected elements include a capacitor, an interconnect, and a buffer. In an alternative embodiment, the plurality of interconnected elements include a buffer, an interconnect and a capacitor.
1. A clock network comprising:
a plurality of interconnected elements formed on a substrate, the plurality of interconnected elements being capable of distributing a clock signal having a plurality of arrival times; and
one or more disconnected elements formed on the substrate, at least one of the one or more disconnected elements including a diode and a capacitor, and wherein at least one of the plurality of interconnected elements is capable of being disconnected from the plurality of interconnected elements to alter at least a first one of the plurality of arrival times and at least one of the one or more disconnected elements is capable of being connected to the plurality of interconnected elements to alter at least a second one of the plurality of arrival times.
2. The clock network of claim 1 , wherein at least one of the one or more disconnected elements is capable of being connected to the plurality of interconnected elements by a modification of a metal level only mask.
3. The clock network of claim 2 , wherein at least one of the plurality of interconnected elements is capable of being disconnected from the plurality of interconnected elements by cutting an interconnect using a focused ion beam.
4. The clock network of claim 1 , wherein the at least one of the one or more disconnected elements including a diode and a capacitor comprises a plurality of capacitors.