Method and apparatus for optimizing flash device erase distribution
View Patent ↗A remapping circuit is connected to a memory. A configuration register is connected to the memory. The configuration register includes performance information for memory blocks in the memory. Also, a system includes a processor, a memory management device is connected to the processor, a display is connected to the processor, a non-volatile memory including a memory blocks is connected to the memory management device, and a register is connected to the non-volatile memory. The memory management device to re-map the non-volatile memory based on information stored in the register.
1. An apparatus comprising:
a memory;
a configuration register to store performance information for memory blocks disposed within the memory, the performance information comprising memory block erase time; and
a remapping circuit coupled to the memory and the configuration register, the remapping circuit to
read the performance information from the configuration register for each memory block,
store the performance information of each memory block in a array,
sort the array according to the performance information, and
remap the memory blocks to store data in a first contiguous portion and to store code in a second contiguous portion based on the sorted array and a memory block erase time performance threshold.
2. The apparatus of claim 1 , wherein the configuration register is disposed within the memory.
3. The apparatus of claim 1 , wherein the performance information further comprises memory block application performance time information.
4. The apparatus of claim 3 , wherein the remapping circuit remaps the memory blocks to store data in a first contiguous portion and to store code in a second contiguous portion based on an application performance time threshold.
5. The apparatus of claim 4 , wherein the memory blocks are physically remapped.
6. The apparatus of claim 1 , wherein the memory is a flash memory.
7. A system comprising:
a processor;
a memory management device coupled to the processor;
a display coupled to the processor;
a non-volatile memory including a plurality of memory blocks coupled to the memory management device; and
a register to store performance information for the memory blocks, the performance information comprising memory block erase time, wherein the memory management device
reads the performance information from the register for each memory block,
stores the performance information of each memory block in an array,
sorts the array according to the performance information, and
re-maps the non-volatile memory to store data in a first contiguous portion and to store code in a second contiguous portion based on the sorted array and a memory block erase time performance threshold.
8. The system of claim 7 , wherein the memory management device operates to re-map the non-volatile memory based on memory block application time performance information.
9. The system of claim 7 , wherein the memory management device physically re-maps the plurality of memory blocks in at least two contiguous segments.
10. The system of claim 7 , wherein the memory management device is one of a memory management unit and a remapping circuit.
11. A machine-accessible medium containing instructions that, when executed, cause a machine to:
store memory block performance information in a register, the performance information comprising memory block erase time for each block of a plurality of blocks in a memory;
read the performance information from the register for each block,
store the performance information of each block in an array,
sort the array according to the performance information; and
remap the memory to store data in a first contiguous portion and to store code in a second contiguous portion based on the sorted array and a memory block erase time performance threshold.
12. The machine-accessible medium of claim 11 , wherein the instruction causing the machine to remap causes the machine to logically remap the plurality of blocks in the memory into at least two contiguous segments.
13. The machine-accessible medium of claim 11 , wherein the instruction causing the machine to remap causes the machine to physically remap the plurality of blocks in the memory into at least two contiguous segments.
14. The machine-accessible medium of claim 11 , further containing instructions, that, when executed cause the machine to:
determine block erase timing performance for each block of the plurality of blocks.
15. The machine-accessible medium of claim 11 , further containing instructions that, when executed, cause the machine to:
determine application timing performance for each block of the plurality of blocks.
16. The machine-accessible medium of claim 11 , wherein the memory is a flash memory.
17. The machine-accessible medium of claim 16 , wherein the register is disposed within the flash memory.
18. The machine-accessible medium of claim 11 , further comprising instructions that, when executed, cause the machine to:
determine a timing threshold for performance;
assign criteria for each block of the plurality of blocks based on the timing threshold;
designate a first set of the plurality of blocks to store code based on the timing threshold; and
designate a second set of the plurality of blocks to store data values based on the timing threshold.
19. A machine-accessible medium containing instructions that, when executed, cause a machine to perform a method comprising:
storing memory block performance information in a register, the performance information comprising memory block programming time for each block of a plurality of blocks in a memory;
reading the performance information from the register for each memory block,
storing the performance information of each memory block in an array,
sorting the performance information of each memory block in an array
remapping the memory to store data in a first contiguous portion and to store code in a second contiguous portion based on the sorted array and a memory block programming time performance threshold.