Two-dimensional pyramid filter architecture
View Patent ↗Implementations of a two-dimensional pyramid filter are disclosed including a two-dimensional pyramid filter architecture of an order 2N−1, where N is a positive integer greater than three. The two-dimensional pyramid filter architecture of order 2N−1 may include one-dimensional pyramid filters of order 2N−1, a first summer circuit; and a second summer circuit. The two dimensional pyramid filter architecture of order 2N−1 may produce, in operation on respective clock cycles, at least a pyramid filtered output signal corresponding to the summation by the first summer circuit of output signals produced by four one-dimensional pyramid filters of order 2N−1, and a pyramid filtered output signal corresponding to an output signal produced by summing signal sample matrices of order [2(N−1)−1] in the second summer circuit. The respective pyramid filtered output signals of the two dimensional pyramid filter architecture may be summed by the third summer circuit on respective clock cycles.
1. An integrated circuit comprising:
a two-dimensional pyramid filter architecture of an order 2N−1, where N is a positive integer greater than three, the two-dimensional pyramid filter architecture of order 2N−1 including,
one-dimensional pyramid filters of order 2 N−1,
a first summer circuit; and
a second summer circuit;
said two dimensional pyramid filter architecture of order 2N−1, in operation, capable of producing, on respective clock cycles, at least the following:
a pyramid filtered output signal corresponding to the summation by the first summer circuit of output signals produced by four one-dimensional pyramid filters of order 2N−1; and
a pyramid filtered output signal corresponding to an output signal produced by summing signal sample matrices of order [2(N−1)−1] in the second summer circuit;
wherein the respective pyramid filtered output signals in said two dimensional pyramid filter architecture are summed by a third summer circuit on respective clock cycles of said two dimensional pyramid filter architecture.
2. The integrated circuit of claim 1 , wherein N is four; and
wherein said two dimensional pyramid filter architecture of order seven, in operation, capable of producing, on respective clock cycles, the pyramid filtered output signals corresponding to the summation of four signal sample matrices p i−1,j−1 5×5 , p i−1,j+1 5×5 , p i+1,j−1 5×5 , p i+1,j+1 5×5 .
3. The integrated circuit of claim 1 , wherein said one-dimensional pyramid filters comprise a sequence of scalable cascaded multiplierless operational units, each of said operational units capable of producing a different order pyramid filtered output signal sample stream.
4. The integrated circuit of claim 1 , wherein said one-dimensional pyramid filters comprise other than one-dimensional multiplierless pyramid filters.
5. The integrated circuit of claim 1 , wherein the first summer circuit sums the output signals produced by eight one-dimensional pyramid filters of order five.
6. The integrated circuit of claim 5 , wherein, of the eight one-dimensional pyramid filters of order five, four are applied row-wise and four are applied column-wise.
7. The integrated circuit of claim 5 , wherein the eight one-dimensional pyramid filters of order five comprise eight one-dimensional multiplierless pyramid filters of order five.
8. The integrated circuit of claim 7 , wherein, of the eight one-dimensional multiplierless pyramid filters of order five, four are applied row-wise and four are applied column-wise.
9. A method of filtering an image using a two-dimensional pyramid filter architecture of order 2N−1, where N is a positive integer greater than three, the two-dimensional pyramid filter architecture of order 2N−1 including one-dimensional pyramid filters of order 2N−1, said method comprising:
summing, on respective clock cycles of said two dimensional pyramid filter architecture, the following:
pyramid filtered output signals corresponding to output signals produced by four one-dimensional pyramid filters of order 2N−1; and
a pyramid filtered output signal corresponding to the summation of signal sample matrices of order [2(N−1)−1].
10. The method of claim 9 , wherein N is four; and
wherein the signal sample matrices comprise four signal sample matrices p i−1,j−1 5×5 , p i−1,j+1 5×5 , p i+1,j−1 5×5 , p i+1,j+1 5×5 .
11. The method of claim 9 , wherein said one-dimensional pyramid filters comprise a sequence of scalable cascaded multiplierless operational units, each of said operational units capable of producing a different order pyramid filtered output signal sample stream.
12. An article comprising: a storage medium, said storage medium having stored thereon instructions, that, when executed result in filtering an image using a two-dimensional pyramid filter architecture of order 2N−1, the two-dimensional pyramid filter architecture of order 2N−1 including one-dimensional pyramid filters of order 2N−1, where N is a positive integer greater than three, by:
summing, on respective clock cycles of said two dimensional pyramid filter architecture, the following:
pyramid filtered output signals corresponding to output signals produced by four one-dimensional pyramid filters of order 2N−1; and
a pyramid filtered output signal corresponding to the summation of signal sample matrices of order [2(N−1)−1].
13. The article of claim 12 , wherein N is four; and
wherein the signal sample matrices comprise four signal sample matrices p i−1,j−1 5×5 , p i−1,j+1 5×5 , p i+1,j−1 5×5 , p i+1,j+1 5×5 .
14. The article of claim 12 , wherein said one-dimensional pyramid filters comprise a sequence of scalable cascaded multiplierless operational units, each of said operational units capable of producing a different order pyramid filtered output signal sample stream.
15. An image processing system comprising:
an image processing unit to filter scanned color images;
said image processing unit including at least one two-dimensional pyramid filter architecture;
said at least one two-dimensional pyramid filter architecture comprising:
a two-dimensional pyramid filter architecture of an order 2N−1, where N is a positive integer greater than three, the two-dimensional pyramid filter architecture of order 2N−1 including one-dimensional pyramid filters of order 2N−1;
said two dimensional pyramid filter architecture of order 2N−1, in operation, capable of producing, on respective clock cycles, at least the following:
a pyramid filtered output signal corresponding to the summation of output signals produced by four one-dimensional pyramid filters of order 2N−1; and
a pyramid filtered output signal corresponding to the summation of signal sample matrices of order [2(N−1)−1];
wherein the respective pyramid filtered output signals in said two dimensional pyramid filter architecture are summed on respective clock cycles of said two dimensional pyramid filter architecture.
16. The system of claim 15 , wherein N is four; and
wherein the signal sample matrices comprise four signal sample matrices p i−1,j−1 5×5 , p i−1,j+1 5×5 , p i+1,j−1 5×5 , p i+1,j+1 5×5 .
17. The system of claim 15 , wherein said one-dimensional pyramid filters comprise a sequence of scalable cascaded multiplierless operational units, each of said operational units capable of producing a different order pyramid filtered output signal sample stream.