Method and apparatus for prediction for fork and join instructions in speculative execution
View Patent ↗A method and apparatus for enabling the speculative forking of a speculative thread is disclosed. In one embodiment, a speculative fork instruction is conditioned by the results of a fork predictor. The fork predictor may issue predictions as to whether or not a speculative thread would execute desirably. The fork predictor may be implemented as a modified branch predictor circuit, and may have execution history updates entered by a determination of whether or not the execution of a speculative thread was or would have been desirable.
1. A processor, comprising:
a fork predictor to issue a prediction whether a fork instruction should be permitted to execute, wherein said fork predictor includes prediction logic to issue said prediction based upon execution history of speculative threads, wherein said fork predictor includes update logic to receive a first calculated determination whether a first one of said speculative threads was executed desirably, and wherein said first calculated determination is performed by executing an update instruction; and
an execution unit to execute said fork instruction responsive to said prediction.
2. The processor of claim 1 , wherein said prediction logic utilizes local history of said speculative threads.
3. The processor of claim 1 , wherein said prediction logic utilizes global history of said speculative threads.
4. The processor of claim 1 , further comprising a retirement unit to transfer said first calculated determination to said update logic.
5. The processor of claim 1 , wherein said update logic is to receive a second calculated determination whether a second one of said speculative threads would have been executed desirably when said second one of said speculative threads was not executed.
6. The processor of claim 1 , wherein said update instruction is part of a join instruction.
7. A method, comprising:
predicting whether a speculative thread will be desirable;
conditionally forking to initiate said speculative thread responsive to said predicting;
determining whether said speculative thread was desirable;
updating state performing said predicting with results of said determining; and
testing whether a processor supports said conditional forking.
8. The method of claim 7 , further comprising joining said speculative thread and a master thread when said speculative thread and said master thread are both complete.
9. The method of claim 8 , wherein said joining is performed with said updating.
10. The method of claim 7 , wherein said determining includes determining whether a non-executed speculative thread would have been desirable.
11. The method of claim 7 , wherein said results include a local history information.
12. The method of claim 7 , wherein said results include a global history information.
13. The method of claim 7 , further comprising initiating a recovery if said determining shows that said speculative execution was not successful.
14. A system, comprising:
a processor including a fork predictor to issue a prediction whether a fork instruction should be permitted to execute and an execution unit to execute said fork instruction responsive to said prediction, wherein said fork predictor includes an update logic to receive a first calculated determination whether a first one of said speculative threads was executed desirably, and wherein said first calculated determination is performed by executing an update instruction;
a chipset coupled to said processor to convey input-output data from an input-output peripheral; and
an input-output peripheral including an audio input-output device.
15. The system of claim 14 , wherein said fork predictor includes a prediction logic to issue said prediction based upon execution history of speculative threads.
16. The system of claim 15 , wherein said prediction logic utilizes local history of said speculative threads.
17. The system of claim 15 , wherein said prediction logic utilizes global history of said speculative threads.
18. The system of claim 15 , further comprising a retirement unit to transfer said first calculated determination to said update logic.
19. The system of claim 15 , wherein said update logic is to receive a second calculated determination whether a second one of said speculative threads would have been executed desirably when said second one of said speculative threads was not executed.
20. The system of claim 15 wherein said update instruction is part of a join instruction.
21. A processor, comprising:
means for predicting whether a speculative thread will be desirable;
means for conditionally forking to initiate said speculative thread responsive to said predicting;
means for determining whether said speculative thread was desirable;
means for updating state performing said predicting with results of said determining; and
means for testing whether a processor supports said conditional forking.
22. The processor of claim 21 , further comprising means for joining said speculative thread and a master thread when said speculative thread and said master thread are both complete.
23. The processor of claim 22 , wherein said means for joining is included in said means for updating.
24. The processor of claim 21 , wherein said means for determining includes means for determining whether a non-executed speculative thread would have been desirable.