Phase comparator and method of controlling power saving operation of the same, and semiconductor integrated circuit
View Patent ↗A power saving operation control method and device for a phase comparator unit are provided. The control device includes: a reference signal frequency dividing unit which divides the frequency of a reference signal to generate a reference frequency divided signal; a comparison signal frequency unit which divides an input signal to generate a comparison frequency divided signal; a phase comparator which compares the phases of the reference frequency divided signal and the comparison frequency divided signal; a canceling signal generator which generates a power saving state canceling signal in accordance with the reference frequency divided signal and the comparison frequency divided signal; a first initializing signal generator which generates a first initializing signal for initializing the reference signal frequency dividing unit in accordance with the power saving state canceling signal; and a second initializing signal generator which generates a second initializing signal for initializing the comparison signal frequency dividing unit in accordance with the power saving state canceling signal.
1. A method of controlling a power saving operation for a phase comparator unit, comprising the steps of:
dividing a frequency of a reference signal to generate a reference frequency divided signal;
dividing a frequency of an input signal to generate a comparison frequency divided signal a phase of which is to be compared with a phase of the reference frequency divided signal;
comparing the phases of the reference frequency divided signal and the comparison frequency divided signal so as to output a comparison result;
generating a power saving state canceling signal in accordance with the reference frequency divided signal and the comparison frequency divided signal;
generating a first initializing signal for initializing the output of the step of dividing the frequency of the reference signal in accordance with the power saving state canceling signal; and
generating a second initializing signal for initializing the output of the step of dividing the frequency of the input signal in accordance with the power saving state canceling signal.
2. The method as claimed in claim 1 , wherein frequency dividing rates used in the step of dividing the frequency of the reference signal and in the step of dividing the frequency of the input signal can be set independently of each other.
3. A power saving operation control circuit for a phase comparator unit, comprising:
a reference signal frequency dividing unit which divides a frequency of a reference signal to generate a reference frequency divided signal;
a comparison signal dividing unit which divides a frequency of an input signal to generate a comparison frequency divided signal whose phase is to be compared with a phase of the reference frequency divided signal;
a phase comparator which compares phases of the reference frequency divided signal and the comparison frequency divided signal so as to output a comparison result;
a canceling signal generator which generates a power saving state canceling signal in accordance with the reference frequency divided signal and the comparison frequency divided signal;
a first initializing signal generator which generates a first initializing signal for initializing the reference signal frequency dividing unit in accordance with the power saving state canceling signal; and
a second initializing signal generator which generates a second initializing signal for initializing the comparison signal frequency dividing unit in accordance with the power saving state canceling signal.
4. The power saving operation control circuit as claimed in claim 3 , wherein frequency dividing rates used in the reference signal frequency dividing unit and in the comparison signal frequency dividing unit can be set independently of each other.
5. A PLL frequency synthesizer comprising:
a phase comparator unit;
a loop filter which receives an output of the phase comparator unit; and
a voltage controlled oscillator which receives an output of the loop filter,
the phase comparator unit comprising:
a reference signal frequency dividing unit which divides a frequency of a reference signal to generate a reference frequency divided signal;
a comparison signal dividing unit which divides a frequency of an output signal of the voltage controlled oscillator to generate a comparison frequency divided signal a phase of which is to be compared with a phase of the reference frequency divided signal;
a phase comparator which compares the phases of the reference frequency divided signal and the comparison frequency divided signal so as to output a comparison result;
a canceling signal generator which generates a power saving state canceling signal in accordance with the reference frequency divided signal and the comparison frequency divided signal;
a first initializing signal generator which generates a first initializing signal for initializing the reference signal frequency dividing unit in accordance with the power saving state canceling signal; and
a second initializing signal generator which generates a second initializing signal for initializing the comparison signal frequency dividing unit in accordance with the power saving state canceling signal.
6. The PLL frequency synthesizer as claimed in claim 5 , wherein frequency dividing rates used in the reference signal frequency dividing unit and in the comparison signal frequency dividing unit can be set independently of each other.
7. A semiconductor integrated circuit including a PLL frequency synthesizer comprising:
a phase comparator unit;
a loop filter which receives an output of the phase comparator unit; and
a voltage controlled oscillator which receives an output of the loop filter,
the phase comparator unit comprising:
a reference signal frequency dividing unit which divides a frequency of a reference signal to generate a reference frequency divided signal;
a comparison signal dividing unit which divides a frequency of an output signal of the voltage controlled oscillator to generate a comparison frequency divided signal a phase of which is to be compared with a phase of the reference frequency divided signal;
a phase comparator which compares the phases of the reference frequency divided signal and the comparison frequency divided signal so as to output a comparison result;
a canceling signal generator which generates a power saving state canceling signal in accordance with the reference frequency divided signal and the comparison frequency divided signal;
a first initializing signal generator which generates a first initializing signal for initializing the reference signal frequency dividing unit in accordance with the power saving state canceling signal; and
a second initializing signal generator which generates a second initializing signal for initializing the comparison signal frequency dividing unit in accordance with the power saving state canceling signal.
8. The semiconductor integrated circuit as claimed in claim 7 , wherein frequency dividing rates used in the reference signal frequency dividing unit and in the comparison signal frequency dividing unit can be set independently of each other.
9. A transmitter-receiver including a PLL frequency synthesizer comprising:
a phase comparator unit;
a loop filter which receives an output of the phase comparator unit; and
a voltage controlled oscillator which receives an output of the loop filter,
the phase comparator unit comprising:
a reference signal frequency dividing unit which divides a frequency of a reference signal to generate a reference frequency divided signal;
a comparison signal dividing unit which divides a frequency of an output signal of the voltage controlled oscillator to generate a comparison frequency divided signal a phase of which is to be compared with a phase of the reference frequency divided signal;
a phase comparator which compares the phases of the reference frequency divided signal and the comparison frequency divided signal so as to output a comparison result;
a canceling signal generator which generates a power saving state canceling signal in accordance with the reference frequency divided signal and the comparison frequency divided signal;
a first initializing signal generator which generates a first initializing signal for initializing the reference signal frequency dividing unit in accordance with the power saving state canceling signal; and
a second initializing signal generator which generates a second initializing signal for initializing the comparison signal frequency dividing unit in accordance with the power saving state canceling signal.
10. The transmitter-receiver as claimed in claim 9 , wherein frequency dividing rates used in the reference signal frequency dividing unit and in the comparison signal frequency dividing unit can be set independently of each other.
11. A method of controlling a power saving operation for a phase comparator unit, comprising the steps of:
dividing a frequency of a reference signal to generate a reference frequency divided signal;
dividing a frequency of an input signal to generate a comparison frequency divided signal a phase of which is to be compared with a phase of the reference frequency divided signal;
comparing the phase of the reference frequency divided signal and the comparison frequency divided signal so as to output a comparison result;
generating a power saving state canceling signal with the reference frequency divided signal so as to output a comparison result; and
generating an initializing signal for initializing the dividing of the frequency of the reference signal or the frequency of the input signal in accordance with the power saving state canceling signal.