IP Library Assignment 036039/0001
Patent Assignment
Reel/Frame 036039/0001

Assignment of Assignor's Interest

Recorded: 2015-06-30 Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CALIFORNIA, 95134
Covered Properties (50)
Phase Comparator and Method of Controlling Power Saving Operation of the Same, and Semiconductor Integrated Circuit
Patent: 7,103,132 →
Application: 09/531,677 →
Method and Apparatus for Pre-Charging Negative Pump Mos Regulation Capacitors
Patent: 7,057,949 →
Application: 10/050,342 →
Semiconductor Device and Liquid Crystal Panel Driver Device
Patent: 7,098,878 →
Application: 10/205,414 →
Publication: US 2003/0098859
Semiconductor Memory Apparatus
Patent: 7,102,928 →
Application: 10/304,762 →
Publication: US 2003/0072175
Method and System for Defining a Redundancy Window Around a Particular Column in a Memory Array
Patent: 7,076,703 →
Application: 10/305,700 →
Memory with Improved Charge-Trapping Dielectric Layer
Patent: 7,074,677 →
Application: 10/307,189 →
Nonvolatile Memory Device for Storing Multi-Bit Data
Patent: 7,057,229 →
Application: 10/341,424 →
Publication: US 2003/0104665
Structure and Method for Reducing Standing Waves in a Photoresist
Patent: 7,070,911 →
Application: 10/350,472 →
Finger Movement Detection Method and Apparatus
Patent: 7,064,743 →
Application: 10/352,943 →
Publication: US 2003/0185425
Protection of Charge Trapping Dielectric Flash Memory Devices from Uv-Induced Charging in Beol Processing
Patent: 7,118,967 →
Application: 10/368,696 →
Method and System for Applying Testing Voltage Signal
Patent: 7,073,104 →
Application: 10/384,856 →
Memory Device Having Improved Periphery and Core Isolation
Patent: 7,078,314 →
Application: 10/407,999 →
Pecvd Silicon-Rich Oxide Layer for Reduced Uv Charging
Patent: 7,060,554 →
Application: 10/617,451 →
Publication: US 2005/0006712
Memory Structure Having Tunable Interlayer Dielectric and Method for Fabricating Same
Patent: 7,078,749 →
Application: 10/618,156 →
Nonvolatile Semiconductor Memory Device Including a Plurality of Blocks and a Sensing Circuit Provided in Each of the Blocks for Comparing Data with a Reference Signal Having a Load Imposed Thereon
Patent: 7,061,809 →
Application: 10/633,535 →
Publication: US 2004/0052119
Memory Device and Method of Simultaneous Fabrication of Core and Periphery of Same
Patent: 7,060,564 →
Application: 10/635,089 →
Structure and Method to Reduce Drain Induced Barrier Lowering
Patent: 7,067,381 →
Application: 10/636,336 →
Low Power Charge Pump
Patent: 7,116,154 →
Application: 10/636,337 →
Publication: US 2005/0030087
Band Distribution Inspecting Device and Band Distribution Inspecting Method
Patent: 7,071,675 →
Application: 10/792,810 →
Publication: US 2005/0057241
Operational Amplifier, Line Driver, and Liquid Crystal Display Device
Patent: 7,081,792 →
Application: 10/811,431 →
Publication: US 2005/0077957
Recessed Channel with Separated Ono Memory Device
Patent: 7,067,377 →
Application: 10/812,703 →
Flash Memory Device and Method of Forming the Same with Improved Gate Breakdown and Endurance
Patent: 7,067,388 →
Application: 10/819,162 →
Method for Providing Short Channel Effect Control Using a Silicide Vss Line
Patent: 7,109,555 →
Application: 10/835,341 →
Uv-Blocking Etch Stop Layer for Reducing Uv-Induced Charging of Charge Storage Layer in Memory Devices in Beol Processing
Patent: 7,091,088 →
Application: 10/861,437 →
A Spread-Spectrum Clock Generator
Patent: 7,098,709 →
Application: 10/866,985 →
Publication: US 2005/0122145
Semiconductor Integrated Circuit Device
Patent: 7,084,658 →
Application: 10/869,075 →
Publication: US 2005/0156615
Alignment Marks with Salicided Spacers Between Bitlines for Alignment Signal Improvement
Patent: 7,098,546 →
Application: 10/869,286 →
Oscillation Circuit and Semiconductor Device Free from the Influence of Source Voltage, Temperature and Fluctuations in the Inverter Threshold Voltage
Patent: 7,068,116 →
Application: 10/877,981 →
Publication: US 2005/0168293
Architecture for Generating Adaptive Arbitrary Waveforms
Patent: 7,072,781 →
Application: 10/885,284 →
Method for Programming Dual Bit Memory Devices to Reduce Complementary Bit Disturbance
Patent: 7,079,423 →
Application: 10/896,299 →
Method for Pulse Erase in Dual Bit Memory Devices
Patent: 7,092,297 →
Application: 10/899,684 →
Horizontal Mos Transistor
Patent: 7,075,159 →
Application: 10/911,630 →
Publication: US 2005/0212012
System and Method for Multi-Bit Flash Reads Using Dual Dynamic References
Patent: 7,103,706 →
Application: 10/933,588 →
Methods and Systems for Reducing Erase Times in Flash Memory Devices
Patent: 7,079,424 →
Application: 10/945,914 →
SO2 Treatment of Oxidized Cuo for Copper Sulfide Formation of Memory Element Growth
Patent: 7,115,440 →
Application: 10/957,247 →
Ion Path Polymers for Ion-Motion Memory
Patent: 7,067,349 →
Application: 10/968,705 →
Semiconductor Device and Method of Manufacturing the Same
Patent: 7,084,037 →
Application: 10/986,652 →
Publication: US 2005/0087778
One Stack with Steam Oxide for Charge Retention
Patent: 7,071,538 →
Application: 11/008,263 →
Memory Cell Containing Copolymer Containing Diarylacetylene Portion
Patent: 7,105,374 →
Application: 11/033,941 →
Semiconductor Device
Patent: 7,091,518 →
Application: 11/043,336 →
Publication: US 2006/0049400
Semiconductor Memory Storage Device and a Redundancy Control Method Therefor
Patent: 7,068,555 →
Application: 11/061,307 →
Publication: US 2005/0185482
Semiconductor Memory Storage Device and Its Redundant Method
Patent: 7,061,816 →
Application: 11/061,365 →
Publication: US 2005/0185483
Constant-Voltage Power Supply Circuit
Patent: 7,092,226 →
Application: 11/076,940 →
Publication: US 2005/0151522
Current Sensing Circuit with a Current-Compensated Drain Voltage Regulation
Patent: 7,099,204 →
Application: 11/087,944 →
Quad Bit Using Hot-Hole Erase for Cbd Control
Patent: 7,113,431 →
Application: 11/091,982 →
Operational Amplifier
Patent: 7,113,041 →
Application: 11/108,815 →
Publication: US 2005/0179496
A Semiconductor Device Having Triple Ldd Structure and Lower Gate Resistance Formed with a Single Implant Process
Patent: 7,084,458 →
Application: 11/120,690 →
Non-Volatile Semiconductor Memory, Semiconductor Device and Charge Pump Circuit
Patent: 7,113,442 →
Application: 11/126,701 →
Publication: US 2005/0254313
Integrated Circuit Test Socket
Patent: 7,108,535 →
Application: 11/180,943 →
Spread Spectrum Clock Generation Circuit, Jitter Generation Circuit and Semiconductor Device
Patent: 7,095,260 →
Application: 11/217,459 →
Publication: US 2005/0285641
Related Assignments (18)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Agreement Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
Assignment of Assignor's Interest Oct 11, 2012
From: SPANSION INC.
To: SPANSION LLC
Reel/Frame 029112/0198 →
Assignment of Assignor's Interest Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
Corrective Assignment to Enclude the Schedules Full List. Previously Recorded on Rell 019069 Frame 0318. Assignor(S) Hereby Confirms the Schedule. Dec 22, 2014
From: SPANSION INC.
To: SPANSION LLC
Reel/Frame 034689/0296 →
Release of Security Interest Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
Security Interest Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
Partial Release of Security Interest in Patents Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
Assignment of Assignor's Interest Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
Assignment of Assignor's Interest Mar 29, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 042108/0880 →
Release of Security Interest Jun 12, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 042769/0227 →
Release of Security Interest Jun 22, 2018
From: MORGAN STANLEY SENIOR FUNDING INC.,
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 046175/0969 →
Assignment of Assignor's Interest Jun 22, 2018
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 046173/0955 →
Assignment of Assignor's Interest May 4, 2019
From: CYPRESS SEMICONDUCTOR CORPORATION
To: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
Reel/Frame 049086/0803 →
Release of Security Interest May 7, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 049109/0573 →
Assignment and Assumption of Security Interest in Intellectual Property Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
Corrective Assignment to Correct the 8647899 Previously Recorded on Reel 035240 Frame 0429. Assignor(S) Hereby Confirms the Security Interst. Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
Release of Security Interest Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
Assignment of Assignor's Interest Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →