Memory structure having tunable interlayer dielectric and method for fabricating same
View Patent ↗According to one embodiment, a memory structure comprises a substrate having a channel region situated between a source region and a drain region. The memory structure further comprises a gate layer formed over the channel region of the substrate, and a tunable interlayer dielectric formed over the gate layer and the substrate. The tunable interlayer dielectric has a transparent state and an opaque state, and comprises a matrix and electrically or magnetically tunable material situated within the matrix. During the transparent state, UV rays can pass through the tunable interlayer dielectric to the gate layer, e.g., to perform a UV erase operation. During the opaque state, UV rays are prevented from passing through the tunable interlayer dielectric to the gate layer, thereby protecting the gate layer against unwanted charge storage and extrinsic damage that may occur during various processes.
1. A memory transistor comprising:
a substrate having a drain region, a source region and a channel region, said channel region being between said source region and said drain region;
a gate layer formed over said channel region of said substrate;
a tunable interlayer dielectric formed over said gate layer and said substrate, said tunable interlayer dielectric comprising a matrix and tunable material situated within said matrix, said tunable interlayer dielectric having a transparent state and an opaque state, said transparent state allowing UV rays to pass through said tunable interlayer dielectric to said gate layer, said opaque state preventing UV rays to pass through said tunable interlayer dielectric to said gate layer.
2. The memory transistor of claim 1 , wherein said tunable material comprises a plurality of liquid crystal droplets, each of said plurality of liquid crystal droplets having a corresponding crystal director, said corresponding crystal director defining a polar orientation of each of said plurality of liquid crystal droplets.
3. The memory transistor of claim 2 , wherein said corresponding crystal director has a random orientation within said matrix during said opaque state.
4. The memory transistor of claim 3 , wherein said opaque state is enabled when an electric field is not applied across said tunable interlayer dielectric.
5. The memory transistor of claim 3 , wherein said opaque state is enabled when a magnetic field is applied across said tunable interlayer dielectric.
6. The memory transistor of claim 2 , wherein said corresponding crystal director has a uniform orientation within said matrix during said transparent state.
7. The memory transistor of claim 6 , wherein said transparent state is enabled when an electric field is applied across said tunable interlayer dielectric.
8. The memory transistor of claim 6 , wherein said transparent state is enabled when a magnetic field is not applied across said tunable interlayer dielectric.
9. The memory transistor of claim 1 , wherein said tunable material is selected from the group consisting of electrically tunable material and magnetically tunable material.
10. The memory transistor of claim 1 , wherein said matrix is polymer.
11. The memory transistor of claim 1 , wherein said gate layer includes a charge storing layer.
12. A memory transistor comprising a substrate having a drain region, a source region and a channel region, said channel region being between said source region and said drain region, said memory transistor further comprising a gate layer formed over said channel region of said substrate, said gate layer including a charge storing layer, said memory transistor characterized by:
a tunable interlayer dielectric formed over said gate layer and said substrate, said tunable interlayer dielectric comprising a matrix and tunable material situated within said matrix, said tunable interlayer dielectric having a transparent state and an opaque state, said transparent state allowing UV rays to pass through said tunable interlayer dielectric to said gate layer, said opaque state preventing UV rays from passing through said tunable interlayer dielectric to said gate layer.
13. The memory transistor of claim 12 , wherein said tunable material comprises a plurality of liquid crystal droplets, each of said plurality of liquid crystal droplets having a corresponding crystal director, said corresponding crystal director defining a polar orientation of each of said plurality of liquid crystal droplets.
14. The memory transistor of claim 13 , wherein, during said opaque state, said corresponding crystal director has a random orientation within said matrix.
15. The memory transistor of claim 13 , wherein, during said transparent state, said corresponding crystal director has a uniform orientation within said matrix.
16. The memory transistor of claim 15 , wherein said transparent state is enabled by providing an electric field through said tunable interlayer dielectric.
17. The memory transistor of claim 12 , wherein said tunable material is selected from the group consisting of electrically tunable material and magnetically tunable material.
18. The memory transistor of claim 12 , wherein said matrix is polymer.
19. The memory transistor of claim 12 , wherein said gate layer includes a charge storing layer.