Patent Assignment
Reel/Frame 019069/0366
Assignment of Assignor's Interest
Recorded: 2007-03-27
Received: 2007-03-27
Pages: 6
Assignor
SPANSION INC.
Executed: 2007-01-31
Assignee
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CA, 94088-3453, UNITED STATES
Covered Properties
(100)
Method for Achieving Increased Control Over Interconnect Line Thickness Across a Wafer and Between Wafers
Application:
11/003,208 →
Patterning for Elongated Vss Contact Flash Memory
Application:
10/968,713 →
Semiconductor Device with Core and Periphery Regions
Application:
10/869,774 →
Ldc Implant for Mirrorbit to Improve Vt Roll-Off and Form Sharper Junction
Application:
10/862,636 →
Cascode Amplifier Circuit for Generating and Maintaining a Fast, Stable and Accurate Bit Line Voltage
Application:
10/844,116 →
Bitline Implant Utilizing Dual Poly
Application:
10/843,289 →
Methods and Apparatus for Wordline Protection in Flash Memory Devices
Application:
10/839,614 →
Method and Apparatus for Eliminating Word Line Bending by Source Side Implantation
Application:
10/839,561 →
Positive Gate Stress During Erase to Improve Retention in Multi-Level, Non-Volatile Flash Memory
Application:
10/839,562 →
Method for Providing Short Channel Effect Control Using a Silicide Vss Line
Application:
10/835,341 →
Memory Device with an Alternating Vss Interconnection
Application:
10/823,972 →
Narrow Wide Spacer
Application:
10/821,312 →
Flash Memory Device and Method of Forming the Same with Improved Gate Breakdown and Endurance
Application:
10/819,162 →
Non -Volatile Memory Device
Application:
10/770,010 →
Bitline Hard Mask Spacer Flow for Memory Cell Scaling
Application:
10/770,673 →
Disposable Hard Mask for Memory Bitline Scaling
Application:
10/770,245 →
Flash Memory Cell with Uv Protective Layer
Application:
10/770,260 →
Flexible Cascode Amplifier Circuit with High Gain for Flash Memory Cells
Application:
10/759,855 →
Hard Mask Spacer for Sublithographic Bitline
Application:
10/729,732 →
Flash Memory Device
Application:
10/726,508 →
Reading Flash Memory
Application:
10/721,643 →
Method and Structure for Protecting Nrom Devices from Induced Charge Damage During Device Fabrication
Application:
10/701,780 →
Sidewall Formation for High Density Polymer Memory Element Array
Application:
10/699,903 →
Non Volatile Charge Trapping Dielectric Memory Cell Structure with Gate Hole Injection Erase
Application:
10/684,890 →
Recessed Channel
Application:
10/683,631 →
Efficient and Accurate Sensing Circuit and Technique for Low Voltage Flash Memory Devices
Application:
10/678,446 →
Memory Device and Method Using Positive Gate Stress to Recover Overerased Cell
Application:
10/677,790 →
Memory Device and Method
Application:
10/677,031 →
Memory Device and Method
Application:
10/677,073 →
Patterning for Elongated Vss Contact on Flash Memory
Application:
10/654,739 →
Test Structure for Determining Electromigration and Interlayer Dielectric Failure
Application:
10/636,162 →
Memory Device Having Silicided Bitlines and Method of Forming the Same
Application:
10/635,781 →
Low Power Charge Pump
Application:
10/636,337 →
Structure and Method to Reduce Drain Induced Barrier Lowering
Application:
10/636,336 →
Memory Device and Method of Simultaneous Fabrication of Core and Periphery of Same
Application:
10/635,089 →
Pecvd Silicon-Rich Oxide Layer for Reduced Uv Charging
Application:
10/617,451 →
Undoped Oxide Liner/Bpsg for Improved Data Retention
Application:
10/617,450 →
Memory Structure Having Tunable Interlayer Dielectric and Method for Fabricating Same
Application:
10/618,156 →
Simultaneous Execution Command Modes in a Flash Memory Device
Application:
10/603,136 →
Non-Volatile Memory Device
Application:
10/459,576 →
Semicondutor Device Having Conductive Structures Formed Near a Gate Electrode
Application:
10/454,517 →
Structure and Method for a Two-Bit Memory Cell
Application:
10/429,140 →
Method of Dual Cell Memory Device Operation for Improved End-of-Life Read Margin
Application:
10/422,092 →
Method of Controlling Program Threshold Voltage Distribution of a Dual Cell Memory Device
Application:
10/422,090 →
Method of Programming Dual Cell Memory Device to Store Multiple Data States Per Cell
Application:
10/413,800 →
Fast, Accurate and Low Power Supply Voltage Booster Using a/D Converter
Application:
10/406,415 →
Circuit for Fast and Accurate Memory Read Operations
Application:
10/387,617 →
Method and System for Applying Testing Voltage Signal
Application:
10/384,856 →
Method and System for Detecting Defective Material Surrounding Flash Memory Cells
Application:
10/384,936 →
Method of Programming a Memory Cell
Application:
10/379,885 →
Memory Array Having Shallow Bit Line with Silicide Contact Portion and Method of Formation
Application:
10/382,731 →
Fast Bandgap Reference Circuit for Use in a Low Power Supply a/D Booster
Application:
10/379,744 →
Method of Forming Core and Periphery Gates Including Two Critical Masking Steps to Form a Hard Mask in a Core Region That Includes a Critical Dimension Less Than Achievable at a Resolution Limit of Lithography
Application:
10/382,744 →
Selection Circuit for Accurate Memory Read Operations
Application:
10/361,378 →
Structure and Method for Suppressing Oxide Encroachment in a Floating Gate Memory Cell
Application:
10/364,569 →
Method for Fabricating Devices in Core and Periphery Semiconductor Regions Using Dual Spacers
Application:
10/361,455 →
Performance in Flash Memory Devices
Application:
10/358,866 →
Compensated Oscillator Circuit for Charge Pumps
Application:
10/358,498 →
Method of Improving Dynamic Reference Tracking for Flash Memory Unit
Application:
10/357,879 →
Method for Reading a Non-Volatile Memory Cell Adjacent to an Inactive Region of a Non-Volatile Memory Cell Array
Application:
10/353,558 →
Novel Non-Volatile Memory Cell and Method of Programming for Improved Data Retention
Application:
10/352,658 →
Memory Circuit Arrangement for Programming a Memory Cell
Application:
10/348,732 →
Dielectric Memory Cell Structure with Counter Doped Channel Region
Application:
10/342,549 →
Flash Memory Cell Programming Method and System
Application:
10/342,585 →
Flash Memory Devices with Oxynitride Dielectric as the Charge Storage Media
Application:
10/342,032 →
Differentially Mis-Aligned Contacts in Flash Arrays to Calibrate Failure Modes
Application:
10/320,910 →
Method and System for Reducing Contact Defects Using Non Conventional Contact Formation Method for Semiconductor Cells
Application:
10/316,569 →
Discontinuous Nitride Structure for Non-Volatile Transistors
Application:
10/315,458 →
Efficient Method to Detect Process Induced Defects in the Gate Stack of Flash Memory Devices
Application:
10/313,676 →
Structure and Method for Reducing Charge Loss in a Memory Cell
Application:
10/313,454 →
Circuit for Accurate Memory Read Operations
Application:
10/313,444 →
System for Programming a Non-Volatile Memory Cell
Application:
10/307,667 →
Method for Fabricating Nitride Memory Cells Using a Floating Gate Fabrication Process
Application:
10/306,529 →
Method and System for Erasing a Nitride Memory Device
Application:
10/306,252 →
Memory Circuit for Suppressing Bit Line Current Leakage
Application:
10/306,080 →
Method of Protecting a Memory Array from Charge Damage During Fabrication
Application:
10/305,750 →
Method and System for Defining a Redundancy Window Around a Particular Column in a Memory Array
Application:
10/305,700 →
Cascode Amplifier Circuit for Producing a Fast, Stable and Accurate Bit Line Voltage
Application:
10/302,672 →
Fabrication of Shallow Trench Isolation Structures with Rounded Corner and Self-Aligned Gate
Application:
10/292,121 →
Method of Alternating Grounded/Floating Poly Lines to Monitor Shorts
Application:
10/288,871 →
Buffer Driver Circuit for Producing a Fast, Stable, and Accurate Reference Voltage
Application:
10/282,459 →
Reference Cell with Various Load Circuits Compensating for Source Side Loading Effects in a Non-Volatile Memory
Application:
10/245,146 →
Precharging Scheme for Reading a Memory Cell
Application:
10/226,912 →
Memory Device and Method of Making
Application:
10/223,920 →
Reflowable-Doped Hdp Film
Application:
10/217,403 →
System and Method for Erase Voltage Control During Multiple Sector Erase of a Flash Memory Device
Application:
10/210,378 →
On-Chip Repair of Defective Address of Core Flash Memory Cells
Application:
10/200,544 →
On-Chip Erase Pulse Counter for Efficient Erase Verify Bist (Built-in-Self-Test) Mode
Application:
10/200,330 →
Method for Semiconductor Wafer Planarization by Isolation Material Growth
Application:
10/190,002 →
Self-Aligned Polysilicon Polish
Application:
10/150,204 →
Method and System for Scaling Nonvolatile Memory Cells
Application:
10/150,255 →
Using a First Liner Layer as a Spacer in a Semiconductor Device
Application:
10/126,207 →
Refresh Scheme for Dynamic Page Programming
Application:
10/119,273 →
Algorithm Dynamic Reference Programming
Application:
10/119,391 →
Precision High-K Intergate Dielectric Layer
Application:
10/117,818 →
Erase Method for a Dual Bit Memory Cell
Application:
10/119,366 →
Overerase Correction Method
Application:
10/099,499 →
Password and Dynamic Protection of Flash Memory Data
Application:
10/091,767 →
Method of Matching Core Cell and Reference Cell Source Resistances
Application:
10/083,789 →
Dummy Gate Process to Reduce the Vss Resistance of Flash Products
Application:
10/081,246 →