Positive gate stress during erase to improve retention in multi-level, non-volatile flash memory
View Patent ↗A new method for improving the accuracy of read-write operations in a multi-level flash memory cell is disclosed. The method reduces the read margin disturbance caused by the accumulation of holes at a tunneling oxide or tunneling oxide-silicon interface underneath a floating gate of the cell by applying a positive stress to the word line after a program-erase cycle.
1. A method of de-trapping trapped charges in a non-volatile multi-level memory device having at least a control gate, and a floating gate, the method comprising:
applying a de-trapping pulse to a control gate of a non-volatile multi-level memory device so as to de-trap positive charges trapped at a tunneling oxide or tunneling oxide-silicon interface underneath a floating gate of the device, whereby the application of the pulse reduces the read disturbance by minimizing a shift of a threshold voltage corresponding to each level of the multi-level memory device.
2. The method of claim 1 wherein the application of the pulse occurs after an erase pulse but before a programming pulse.
3. The method of claim 1 wherein the de-trapping pulse has a duration of about ten milliseconds.
4. The method of claim 1 wherein the de-trapping pulse has an amplitude of about 9 volts.
5. The method of claim 1 wherein the de-trapping pulse voltage is positive with respect to the substrate.
6. A computer program embodied on a computer readable medium for de-trapping trapped charges in a non-volatile multi-level memory device having at least a control gate, and a floating gate, the computer program comprising:
code for applying a de-trapping pulse to a control gate of a non-volatile multi-level memory device so as to de-trap positive charges trapped at a tunneling oxide or tunneling oxide-silicon interface underneath a floating gate of the device, whereby the application of the pulse reduces the read disturbance by minimizing a shift of a threshold voltage corresponding to each level of the multi-level memory device.
7. The computer program of claim 6 wherein the application of the pulse occurs after an erase pulse but before a programming pulse.
8. The computer program of claim 6 wherein the de-trapping pulse has a duration of about ten milliseconds.
9. The computer program of claim 6 wherein the de-trapping pulse has an amplitude of about 9 volts.
10. The computer program of claim 6 wherein the de-trapping pulse voltage is positive with respect to the substrate.
11. A system for de-trapping trapped charges in a non-volatile multi-level memory device having at least a control gate, and a floating gate, the system comprising:
means for applying a de-trapping pulse to a control gate of a non-volatile multi-level memory device so as to de-trap positive charges trapped at a tunneling oxide or tunneling oxide-silicon interface underneath a floating gate of the device, whereby the application of the pulse reduces the read disturbance by minimizing a shift of a threshold voltage corresponding to each level of the multi-level memory device.