Patent Assignment
Reel/Frame 019069/0372
Assignment of Assignor's Interest
Recorded: 2007-03-27
Received: 2007-03-27
Pages: 6
Assignor
SPANSION INC.
Executed: 2007-01-31
Assignee
SPANSION LLC
915 DEGUIGNE DRIVE, P.O. BOX 3453, MAIL STOP 250, SUNNYVALE, CA, 94088-3453, UNITED STATES
Covered Properties
(25)
Method for Achieving Increased Control Over Interconnect Line Thickness Across a Wafer and Between Wafers
Application:
11/003,208 →
Ramped Soft Programming for Control of Erase Voltage Distributions in Flash Memory Devices
Application:
10/981,833 →
Patterning for Elongated Vss Contact Flash Memory
Application:
10/968,713 →
Ramp Source Hot-Hole Programming for Trap Based Non-Volatile Memory Devices
Application:
10/863,933 →
Memory Device and Methods of Using Negative Gate Stress to Correct Over-Erased Memory Cells
Application:
10/863,673 →
Ldc Implant for Mirrorbit to Improve Vt Roll-Off and Form Sharper Junction
Application:
10/862,636 →
Bitline Implant Utilizing Dual Poly
Application:
10/843,289 →
Flash Memory Cell and Methods for Programming and Erasing
Application:
10/841,850 →
Methods and Apparatus for Wordline Protection in Flash Memory Devices
Application:
10/839,614 →
Method and Apparatus for Eliminating Word Line Bending by Source Side Implantation
Application:
10/839,561 →
Positive Gate Stress During Erase to Improve Retention in Multi-Level, Non-Volatile Flash Memory
Application:
10/839,562 →
Semiconductor Component and Method of Manufacture
Application:
10/795,924 →
Structure for Increasing Drive Current in a Memory Array and Related Method
Application:
10/759,809 →
Flexible Cascode Amplifier Circuit with High Gain for Flash Memory Cells
Application:
10/759,855 →
Pocket Implant for Complementary Bit Disturb Improvement and Charging Improvement of Sonos Memory Cell
Application:
10/755,740 →
Narrow Bitline Using Safier for Mirrorbit
Application:
10/755,430 →
Hard Mask Spacer for Sublithographic Bitline
Application:
10/729,732 →
Neutron Detecting Device
Application:
10/728,510 →
Minimization of Fg-Fg Coupling in Flash Memory
Application:
10/700,414 →
Efficient and Accurate Sensing Circuit and Technique for Low Voltage Flash Memory Devices
Application:
10/678,446 →
Circuit and Technique for Accurately Sensing Low Voltage Flash Memory Devices
Application:
10/679,179 →
Memory Cell Structure Having Nitride Layer with Reduced Charge Loss and Method for Fabricating Same
Application:
10/655,179 →
Patterning for Elongated Vss Contact on Flash Memory
Application:
10/654,739 →
A Method of Fabricating a Dual-Level Stacked Flash Memory Cell with a Mosfet Storage Transistor
Application:
10/634,042 →
Fast, Accurate and Low Power Supply Voltage Booster Using a/D Converter
Application:
10/406,415 →