Patterning for elliptical Vss contact on flash memory
View Patent ↗A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.
1. A method of forming a contact in a flash memory device that improves the depth of focus (DOF) margin and the overlay margin between a plurality of stacked gate layers and the respective contact, comprising the steps of:
forming a plurality of stacked gate layers on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers;
depositing an interlayer insulating layer over the plurality of stacked gate layers;
patterning a contact hole between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers, wherein the contact hole is an elliptical shape having a major axis and a minor axis, and the contact hole is dimensioned along the major axis so as to maintain focus of an image of the contact hole as the minor axis is reduced in size towards a DOF limit; and
depositing a conductive layer in the contact hole.
2. The method of claim 1 , wherein the step of patterning a contact hole between a first stacked gate layer and a second stacked gate layer includes aligning the major axis of the contact hole substantially parallel to the predefined direction of the stacked gate layers.
3. The method of claim 1 , wherein the step of patterning a contact hole between a first stacked gate layer and a second stacked gate layer includes aligning the minor axis of the contact hole substantially perpendicular to the predefined direction of the stacked gate layers.
4. The method of claim 1 , further comprising the step of:
removing a portion of the conductive layer that is outside the contact hole to leave the conductive layer in the contact hole.
5. The method of claim 1 , wherein the step of patterning a contact hole between a first stacked gate layer and a second stacked gate layer includes forming the minor axis of the contact hole to be about 71 percent to about 90 percent of a major axis of the contact hole.
6. A flash memory device, comprising:
a plurality of stacked gate layers, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers; and
a contact formed between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers, wherein the contact is formed in an elliptical shape.
7. The flash memory device of claim 6 , wherein the contact includes a major axis, and the major axis is substantially parallel to the predefined direction of the stacked gate layers.
8. The flash memory device of claim 6 , wherein the contact includes a minor axis, and the minor axis is substantially perpendicular to the predefined direction of the stacked gate layers.
9. The flash memory device of claim 6 , wherein the contact is a V ss contact.
10. The flash memory device claim 6 , wherein a minor axis of the contact is about 71 percent to about 90 percent of a major axis of the contact.