Hard mask spacer for sublithographic bitline
View Patent ↗A technique for forming at least part of an array of a dual bit memory core is disclosed. Spacers are utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.
1. A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising:
forming a charge trapping dielectric layer over the substrate;
forming a hardmask over the charge trapping dielectric layer;
patterning the hardmask to form a plurality of hardmask features having a first spacing therebetween;
forming a spacer material over the patterned hardmask;
patterning the spacer material to form spacers adjacent the hardmask features and defining a second spacing between the hardmask features that is less than the first spacing;
performing a bitline implant through the charge trapping dielectric to establish buried bitlines within the substrate having a width corresponding to the second spacing;
removing the entire patterned hardmask and all the spacers associated with the patterned hardmask;
forming a wordline material over the charge trapping dielectric layer; and
patterning the wordline material to form wordlines that overlie the bitlines.
2. The method of claim 1 , wherein the substrate is p-type and the bitline implant is performed with an n-type dopant, and wherein the spacers inhibit the dopant from being implanted there-under, the spacers thus serving to establish bitlines that are narrower than the first spacing.
3. The method of claim 2 , wherein the bitline implant dopant includes Arsenic.
4. The method of claim 3 , wherein the bitline implant is performed at a concentration of between about 5E14 and 2E15 atoms/cm3.
5. The method of claim 3 , wherein the bitline implant is performed at an energy level of between about 40 to 70 KeV.
6. The method of claim 1 , wherein forming a charge trapping dielectric layer comprises:
forming a first insulating layer over the semiconductor substrate;
forming a charge trapping layer over the first insulating layer; and
forming a second insulating layer over the charge trapping layer.
7. The method of claim 6 , wherein the first and second insulating layers comprise silicon dioxide.
8. The method of claim 6 , wherein the charge-trapping layer comprises silicon nitride.
9. The method of claim 6 , wherein the first insulating layer is formed to a thickness of about 70 Angstroms or less.
10. The method of claim 6 , wherein the charge trapping layer is formed to a thickness of between about 60 to 80 Angstroms.
11. The method of claim 6 , wherein the second insulating layer is formed to a thickness of about 100 Angstroms or less.
12. The method of claim 6 , further comprising:
removing the second insulating layer; and
re-applying the second insulating layer to a thickness of about 100 Angstroms or less.
13. The method of claim 12 , wherein the removed second insulating layer layer is initially formed to a thickness of between about 100 to 200 Angstroms.
14. The method of claim 1 , wherein at least one of the hardmask and spacers are formed of nitride or poly-based material(s).
15. The method of claim 2 , wherein the implanted bitlines have a width of between about 40 to 100 nano-meters or less.
16. The method of claim 1 , wherein the wordlines are oriented at substantially right angles relative to the buried bitlines.
17. The method of claim 1 , comprising:
performing a threshold adjustment implant into the semiconductor substrate prior to forming the charge trapping dielectric layer.
18. The method of claim 17 , wherein the substrate is doped with a p-type dopant and the threshold adjustment implant includes at least one of a greater concentration of and a higher energy implant of the same or different p-type dopant.
19. The method of claim 18 , wherein the threshold adjustment implant includes Boron.
20. The method of claim 1 , wherein the substrate comprises silicon.
21. A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising:
forming at least a portion of a charge trapping dielectric layer over the substrate;
forming a layer of sacrificial material over the portion of the charge trapping dielectric layer;
forming a hardmask over the sacrificial layer;
patterning the hardmask to form a plurality of hardmask features having a first spacing therebetween;
forming a spacer material over the patterned hardmask;
patterning the spacer material to form spacers adjacent the hardmask features and defining a second spacing between the hardmask features that is less than the first spacing;
performing a bitline implant through the portion of the charge trapping dielectric layer to establish buried bitlines within the substrate having a width corresponding to the second spacing;
removing the patterned hardmask and spacers; and
forming a remaining portion of the charge trapping layer over the portion of the charge trapping dielectric layer.
22. The method of claim 21 , wherein forming at least a portion of a charge trapping dielectric layer comprises:
forming a first insulating layer over the semiconductor substrate; and
forming a charge trapping layer over the first insulating layer.
23. The method of claim 22 , wherein forming a layer of sacrificial material comprises:
forming a second insulating layer over the charge trapping layer.
24. The method of claim 23 , wherein the first and second insulating layers comprise silicon dioxide.
25. The method of claim 22 , wherein the charge-trapping layer comprises silicon nitride.
26. The method of claim 22 , wherein the first insulating layer is formed to a thickness of about 70 Angstroms or less.
27. The method of claim 22 , wherein the charge trapping layer is formed to a thickness of between about 60 to 80 Angstroms.
28. The method of claim 21 , wherein the remaining portion of the charge trapping layer is formed to a thickness of about 100 Angstroms or less.
29. The method of claim 21 , wherein the layer of sacrificial material is formed to a thickness of between about 100 to 200 Angstroms.
30. The method of claim 21 , wherein the implanted bitlines have a width of between about 40 to 100 nano-meters or less.
31. The method of claim 21 , further comprising:
forming a wordline material over the charge trapping dielectric layer; and
patterning the wordline material to form wordlines that overlie the bitlines.