Method of fabricating a dual-level stacked flash memory cell with a MOSFET storage transistor
View Patent ↗The present invention relates to methods of fabricating dual-level flash memory cells. A first active region and a second active region are formed in a substrate. A trench is formed in the substrate between the first active region and the second active region. A first insulator dielectric is formed on the substrate and within the trench forming a vertical structure. A first poly layer is formed on the first insulator dielectric. A second insulator dielectric is formed on at least a portion of the first poly layer. A second poly layer is formed on the second insulator dielectric.
1. A method of fabricating a dual level memory cell comprising:
forming a first active region and a second active region in a substrate;
forming a trench in the substrate between the first active region and the second active region;
forming a first insulator dielectric on the substrate that forms a vertical structure within the trench;
forming a first poly layer on the first insulator;
forming a second insulator dielectric on at least a portion of the first poly layer; and
forming a second poly layer on the second insulator dielectric.
2. A method of fabricating a dual level memory cell comprising:
forming a first active region and a second active region in a substrate;
forming a first insulator dielectric on the substrate;
forming a first poly layer on the first insulator dielectric;
forming a second insulator dielectric on at least a portion of the first poly layer; and
forming a second poly layer on the second insulator dielectric;
forming a trench in the substrate between the first active region and the second active region prior to forming the first insulator dielectric such that a vertical structure is formed by the first insulator dielectric; and
wherein the vertical structure is V-shaped.
3. The method of claim 1 , wherein forming the first insulator dielectric comprises forming a first oxide layer on the substrate, forming nitride on the first oxide layer, and forming a second oxide layer on the nitride.
4. The method of claim 1 , wherein the first active region and the second active region are formed to be n-type and the substrate is p-type.
5. The method of claim 1 , wherein the vertical structure is U-shaped.