Efficient and accurate sensing circuit and technique for low voltage flash memory devices
View Patent ↗An exemplary sensing circuit comprises a first transistor connected to a first node, where a target memory cell has a drain capable of being connected to the first node through a selection circuit during a read operation involving the target memory cell. The sensing circuit further comprises a decouple circuit which is connected to the first transistor. The decouple circuit includes a second transistor having a gate coupled to a gate of the first transistor. The decouple circuit further has a decouple coefficient (N) greater than 1. The drain of the second transistor is connected at a second node to a reference voltage through a bias resistor. With the arrangement, the drain of the second transistor generates a sense amp input voltage at the second node such that the sense amp input voltage is decoupled from the first node.
1. A sensing circuit for a target memory cell, said sensing circuit comprising:
said target memory cell having a drain capable of being connected to a first node through a selection circuit during a read operation involving said target memory cell, said target memory cell drawing a target memory cell current when activated during said read operation;
a first transistor being connected to said first node;
a decouple circuit being connected to said first transistor, said decouple circuit including a second transistor having a gate width greater than a gate width of said first transistor, a gate of said second transistor being coupled to a gate of said first transistor, said decouple circuit further having a decouple coefficient (N) greater than 1, a drain of said second transistor being connected at a second node to a reference voltage through a bias resistor, said drain of said second transistor generating a sense amp input voltage at said second node such that said sense amp input voltage is decoupled from said first node.
2. The sensing circuit of claim 1 wherein said gate of said second transistor is N times wider than said gate of said first transistor.
3. The sensing circuit of claim 1 wherein said decouple circuit draws a mirror current N times larger than said target memory cell current.
4. The sensing circuit of claim 1 wherein said first transistor comprises a first PFET, and said second transistor comprises a second PFET, said gate of said first PFET connected to a drain of said first PFET, a source of said first PFET and a source of said second PFET being connected to a supply voltage.
5. The sensing circuit of claim 1 wherein said reference voltage is ground.
6. The sensing circuit of claim 1 wherein said target memory cell is capable of storing four charge levels.
7. The sensing circuit of claim 6 wherein said four charge levels comprises a first charge level drawing approximately 0 microamperes during said read operation, a second charge level drawing approximately 10 microamperes during said read operation, a third charge level drawing approximately 15 microamperes during said read operation, and a fourth charge level drawing approximately 20 microamperes during said read operation.
8. A multi-level charge memory device comprising:
a target memory cell having a drain capable of being connected to a first node through a selection circuit during a read operation involving said target memory cell, said target memory cell drawing a target memory cell current when activated during said read operation; and
a sensing circuit comprising a first transistor connected to a decouple circuit, said first transistor being connected to said first node, said decouple circuit including a second transistor having a gate width greater than a gate width of said first transistor, a gate of said second transistor being coupled to a gate of said first transistor, said decouple circuit further having a decouple coefficient (N) greater than 1, a drain of said second transistor being connected at a second node to a reference voltage through a bias resistor, said drain of said second transistor generating a sense amp input voltage at said second node such that said sense amp input voltage is decoupled from said first node.
9. The multi-level charge memory device of claim 8 wherein said gate of said second transistor is N times wider than said gate of said first transistor.
10. The multi-level charge memory device of claim 8 wherein said decouple circuit draws a mirror current N times larger than said target memory cell current.
11. The multi-level charge memory device of claim 8 wherein said first transistor comprises a first PFET, and said second transistor comprises a second PFET, said gate of said first PFET connected to a drain of said first PFET, a source of said first PFET and a source of said second PFET being connected to a supply voltage.
12. The multi-level charge memory device of claim 8 wherein said reference voltage is ground.
13. The multi-level charge memory device of claim 8 wherein said target memory cell is capable of storing four charge levels.
14. The multi-level charge memory device of claim 13 wherein said four charge levels comprises a first charge level drawing approximately 0 microamperes during said read operation, a second charge level drawing approximately 10 microamperes during said read operation, a third charge level drawing approximately 15 microamperes during said read operation, and a fourth charge level drawing approximately 20 microamperes during said read operation.
15. A sensing circuit for a target memory cell, said target memory cell having a drain capable of being connected to a first node through a selection circuit during a read operation involving said target memory cell, said target memory cell drawing a target memory cell current when activated during said read operation, a first transistor being connected to said first node, said sensing circuit being characterized by:
a decouple circuit being connected to said first transistor, said decouple circuit including a second transistor having a gate width greater than a gate width of said first transistor, a gate of said second transistor being coupled to a gate of said first transistor, said decouple circuit further having a decouple coefficient (N) greater than 1, a drain of said second transistor being connected at a second node to a reference voltage through a bias resistor, said drain of said second transistor generating a sense amp input voltage at said second node such that said sense amp input voltage is decoupled from said first node.
16. The sensing circuit of claim 15 wherein said gate of said second transistor is N times wider than said gate of said first transistor.
17. The sensing circuit of claim 15 wherein said decouple circuit draws a mirror current N times larger than said target memory cell current.
18. The sensing circuit of claim 15 wherein said first transistor comprises a first PFET, and said second transistor comprises a second PFET, said gate of said first PFET connected to a drain of said first PFET, a source of said first PFET and a source of said second PFET being connected to a supply voltage.
19. The sensing circuit of claim 15 wherein said reference voltage is ground.
20. The sensing circuit of claim 15 wherein said target memory cell is capable of storing four charge levels.