Memory cell structure having nitride layer with reduced charge loss and method for fabricating same
View Patent ↗According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.
1. A memory cell structure comprising:
a semiconductor substrate;
a first silicon oxide layer situated over said semiconductor substrate;
a charge storing layer formed from nitrogen radicals and situated over said first silicon oxide layer, said charge storing layer comprising silicon nitride having reduced hydrogen content, said reduced hydrogen content reducing charge loss in said charge storing layer;
a second silicon oxide layer situated over said charge storing layer;
a gate layer situated over said second silicon oxide layer.
2. The memory cell structure of claim 1 , further comprising:
said first silicon oxide layer, said charge storing layer, said second silicon oxide layer, and said gate layer forming a gate stack, said gate stack having a sidewall;
a spacer adjacent to said sidewall of said gate stack, said spacer comprising silicon nitride having reduced hydrogen content, said reduced hydrogen content reducing charge loss in said charge storing layer.
3. The memory cell structure of claim 2 , wherein said gate stack is situated over a channel region in said semiconductor substrate, said channel region situated between a first terminal region and a second terminal region.
4. The memory cell structure of claim 1 , wherein said charge storing layer has a hydrogen content less than 1.0 atomic percent.
5. The memory cell structure of claim 1 , wherein said charge storing layer has a hydrogen content between 0 and 0.5 atomic percent.
6. The memory cell structure of claim 1 , wherein said charge storing layer is capable of storing two bits.
7. A memory cell structure comprising:
a semiconductor substrate, a first silicon oxide layer situated over said semiconductor substrate, a charge storing layer situated over said first silicon oxide layer, a second silicon oxide layer situated over said charge storing layer, a gate layer situated over said second silicon oxide layer, said memory cell structure characterized by:
said charge storing layer formed from nitrogen radicals and comprising silicon nitride having reduced hydrogen content;
said reduced hydrogen content reducing charge loss in said charge storing layer.
8. The memory cell structure of claim 7 , further comprising said first silicon oxide layer, said charge storing layer, said second silicon oxide layer, and said gate layer forming a gate stack, said gate stack having a sidewall;
a spacer adjacent to said sidewall of said gate stack, said spacer comprising silicon nitride having reduced hydrogen content, said reduced hydrogen content reducing charge loss in said charge storing layer.
9. The memory cell structure of claim 7 , wherein said gate stack is situated over a channel region in said semiconductor substrate, said channel region situated between a first terminal region and a second terminal region.
10. The memory cell structure of claim 7 , wherein said charge storing layer has a hydrogen content less than 1.0 atomic percent.
11. The memory cell structure of claim 7 , wherein said charge storing layer has a hydrogen content between 0 to 0.5 atomic percent.
12. The memory cell structure of claim 7 , wherein said charge storing layer is capable of storing two bits.