Methods and apparatus for wordline protection in flash memory devices
View Patent ↗Methods and structures are presented for protecting flash memory wordlines and memory cells from process-related charging during fabrication. Undoped polysilicon is formed at the ends of doped polysilicon wordlines to create resistors through which process charges are discharged to a doped polysilicon discharge structure coupled with a substrate. The wordlines, resistors, and the discharge structure can be formed as a unitary patterned polysilicon structure, where the wordline and discharge portions are selectively doped to be conductive and the resistor portions are substantially undoped to provide a resistance high enough to allow normal cell operation after fabrication while providing a discharge path for process-related charging during fabrication.
1. A method of fabricating a wordline structure for a flash memory cell, the method comprising:
forming a conductive wordline structure above a floating gate or charge trapping material of at least one flash memory cell, where the word line structure is formed after one or more source/drain implantation processes have been performed to establish one or more conductive bitlines within a semiconductor substrate upon which the flash memory cell is formed; and
forming a resistor concurrently with the conductive wordline structure and between the conductive wordline structure and the substrate, where the resistor is also formed after the one or more source/drain implantation processes have been performed.
2. The method of claim 1 , wherein the resistor is formed prior to interconnect processing.
3. The method of claim 1 , wherein forming the conductive wordline structure comprises forming doped polysilicon above the floating gate or charge trapping material, and wherein forming the resistor comprises forming substantially undoped polysilicon connected to the conductive wordline structure.
4. The method of claim 3 , wherein forming the doped and substantially undoped polysilicon comprises:
depositing a polysilicon layer;
patterning the polysilicon layer to define a polysilicon wordline portion over the floating gate or charge trapping material and a polysilicon resistor portion connected to the polysilicon wordline portion; and
doping the polysilicon wordline portion.
5. The method of claim 1 , wherein forming the conductive wordline structure comprises forming a first doped polysilicon structure above the floating gate or charge trapping material, and wherein forming the resistor comprises forming a second doped polysilicon structure spaced from the first doped polysilicon structure and forming a substantially undoped polysilicon structure between the first and second doped polysilicon structures.
6. The method of claim 5 , wherein forming the doped and substantially undoped polysilicon structures comprises:
depositing a polysilicon layer;
patterning the polysilicon layer to define a polysilicon wordline portion over the floating gate or charge trapping material, a polysilicon discharge portion spaced from the polysilicon wordline portion, and a polysilicon resistor portion between the polysilicon wordline portion and the polysilicon discharge portion; and
doping the polysilicon wordline portion and the polysilicon discharge portion.
7. The method of claim 5 , wherein the second doped polysilicon structure is formed over a thin dielectric above the substrate.
8. The method of claim 7 , further comprising electrically coupling the second doped polysilicon structure to the substrate.
9. The method of claim 5 , further comprising electrically coupling the second doped polysilicon structure to the substrate.
10. The method of claim 5 , wherein the doped and substantially undoped polysilicon structures are formed concurrently.
11. The method of claim 5 , wherein the doped and substantially undoped polysilicon structures are formed prior to interconnect processing.
12. The method of claim 1 , wherein the resistor is electrically coupled between the conductive wordline structure and the substrate prior to interconnect processing.
13. A method of protecting wordline structures in a flash memory array, the method comprising:
forming a plurality of polysilicon resistor structures individually coupled with a plurality of conductive wordlines in a memory array, where the resistor structures and wordlines are formed concurrently and after one or more source/drain implantation processes have been performed to establish one or more conductive bitlines within a semiconductor substrate upon which the flash memory array is formed; and
coupling the plurality of polysilicon resistor structures to the substrate.
14. The method of claim 13 , wherein forming the plurality of polysilicon resistor structures comprises:
depositing a polysilicon layer;
patterning the polysilicon layer to define a plurality of polysilicon wordline portions, a polysilicon discharge portion spaced from the polysilicon wordline portions, and a plurality of polysilicon resistor portions individually extending between the polysilicon discharge portion and the plurality of polysilicon wordline portions; and
doping the polysilicon discharge portion and the plurality of polysilicon wordline portions.
15. The method of claim 13 , wherein coupling the resistor structures to the substrate comprises forming a conductive discharge structure over a thin dielectric above the substrate and electrically coupling the discharge structure to the plurality of polysilicon resistor structures.
16. The method of claim 13 , wherein coupling the resistor structures to the substrate comprises:
forming a conductive discharge structure;
electrically coupling the discharge structure to the plurality of polysilicon resistor structures; and
electrically coupling the discharge structure to the substrate.
17. A method of protecting memory cells in a flash memory array, the method comprising:
performing one or more source/drain implantation processes to form a plurality of addressable bitlines of a memory array in a substrate;
concurrently forming a plurality of polysilicon resistor structures and a plurality of addressable wordlines of a memory array, wherein the resistor structures and addressable word lines are formed after the addressable bitlines have been formed; and
coupling each addressable wordline to the substrate via an individual one of the polysilicon resistor structures.
18. The method of claim 17 , wherein forming the plurality of polysilicon resistor structures and a plurality of addressable wordlines comprises:
depositing a polysilicon layer;
patterning the polysilicon layer to define a plurality of polysilicon wordline portions, a polysilicon discharge portion spaced from the polysilicon wordline portions, and a plurality of polysilicon resistor portions individually extending between the polysilicon discharge portion and the plurality of polysilicon wordline portions; and
doping the polysilicon discharge portion and the plurality of polysilicon wordline portions.