Patent Assignment
Reel/Frame 036038/0467
Assignment of Assignor's Interest
Recorded: 2015-06-30
Received: 2015-06-30
Pages: 153
Assignor
SPANSION, LLC
Executed: 2015-06-01
Assignee
CYPRESS SEMICONDUCTOR CORPORATION
198 CHAMPION COURT, SAN JOSE, CA, 95134, UNITED STATES
Covered Properties
(69)
Control Circuit and Control Method for Dc-Dc Converter
Application:
11/374,196 →
Nonvolatile Semiconductor Memory Device Performing Erase Operation That Creates Narrow Threshold Distribution
Application:
11/358,206 →
Semiconductor Device and Method of Controlling Said Semiconductor Device
Application:
11/290,001 →
Method and Apparatus for Setting Operational Information of a Non-Volatile Memory
Application:
11/259,873 →
Semiconductor Memory Device and Manufacturing Method Thereof
Application:
11/247,328 →
Semiconductor Memory Devices and Methods for Fabricating the Same
Application:
11/243,752 →
Charge Sharing Technique During Flash Memory Programming
Application:
11/229,530 →
Methods and Systems for Reducing the Threshold Voltage Distribution Following a Memory Cell Erase
Application:
11/193,391 →
Power Interconnect Structure for Balanced Bitline Capacitance in a Memory Array
Application:
11/173,930 →
Semiconductor Device and Source Voltage Control Method
Application:
11/165,008 →
Multiphase Dc-Dc Converter
Application:
11/145,232 →
Flexible Latency in Flash Memory
Application:
11/135,231 →
Multi-Phase Dc-Dc Converter and Control Circuit for Multi-Phase Dc-Dc Converter
Application:
11/121,084 →
Multi-Chip Module and Method of Manufacture
Application:
11/116,571 →
Semiconductor Device and Method for Writing Data into the Semiconductor Device
Application:
11/090,716 →
Temperature Compensation of Thin Film Diode Voltage Threshold in Memory Sensing Circuit
Application:
11/086,884 →
Decoder for Memory Device
Application:
11/076,252 →
System and Method for Erasing a Memory Cell
Application:
11/062,641 →
Semiconductor Memory Storage Device and Its Control Method
Application:
11/064,054 →
Current-Voltage Converter Circuit and Its Control Method
Application:
11/061,119 →
Buried Word Line Memory Integrated Circuit System
Application:
11/045,694 →
Multi-Level Ono Flash Program Algorithm for Threshold Width Control
Application:
11/034,642 →
Method for Achieving Increased Control Over Interconnect Line Thickness Across a Wafer and Between Wafers
Application:
11/003,208 →
Selective Polymer Growth for Memory Cell Fabrication
Application:
11/000,740 →
Multi Bit Program Algorithm
Application:
10/982,296 →
Circuit for Detecting Difference in Capacitance
Application:
10/981,795 →
Memory Cell with Plasma-Grown Oxide Spacer for Reduced Dibl and Vss Resistance and Increased Reliability
Application:
10/981,174 →
Method of Making a Memory Cell
Application:
10/979,516 →
Semiconductor Device Having Output Circuit Adaptively Suppressing Sso Noise
Application:
10/975,831 →
Patterning for Elongated Vss Contact Flash Memory
Application:
10/968,713 →
Mos Capacitor Device
Application:
10/965,856 →
Level Conversion Circuit
Application:
10/948,524 →
Semiconductor Device and Microcontroller
Application:
10/947,538 →
Capacitance Difference Detecting Circuit and Mems Sensor
Application:
10/942,127 →
Method of Forming Copper Sulfide Layer Over Substrate
Application:
10/939,897 →
Method and Structure of Memory Element Plug with Conductive Ta Removed from Sidewall at Region of Memory Element Film
Application:
10/939,773 →
Sonos Memory with Inversion Bit-Lines
Application:
10/928,582 →
Polymer Memory Device with Variable Period of Retention Time
Application:
10/919,572 →
Method to Improve Yield and Simplify Operation of Polymer Memory Cells
Application:
10/919,872 →
Using Thin Undoped Teos with Bpteos Ild or Bpteos Ild Alone to Improve Charge Loss and Contact Resistance in Multi Bit Memory Devices
Application:
10/917,562 →
Memory Cell with Reduced Dibl and Vss Resistance
Application:
10/915,771 →
Flash Memory Unit and Method of Programming a Flash Memory Device
Application:
10/909,693 →
Switchable Memory Diode - a New Memory Device
Application:
10/883,350 →
Semiconductor Device with Core and Periphery Regions
Application:
10/869,774 →
Ldc Implant for Mirrorbit to Improve Vt Roll-Off and Form Sharper Junction
Application:
10/862,636 →
Method and System for Improving the Topography of a Memory Array
Application:
10/861,575 →
Method of Determining Voltage Compensation for Flash Memory Devices
Application:
10/860,450 →
Method and Device for Reducing Interface Area of a Memory Device
Application:
10/859,369 →
Flash Memory Cell and Methods for Programming and Erasing
Application:
10/841,850 →
Methods and Apparatus for Wordline Protection in Flash Memory Devices
Application:
10/839,614 →
Method and Apparatus for Eliminating Word Line Bending by Source Side Implantation
Application:
10/839,561 →
Positive Gate Stress During Erase to Improve Retention in Multi-Level, Non-Volatile Flash Memory
Application:
10/839,562 →
Disposable Hard Mask for Memory Bitline Scaling
Application:
10/770,245 →
Flexible Cascode Amplifier Circuit with High Gain for Flash Memory Cells
Application:
10/759,855 →
Electrostatic Discharge Performance of a Silicon Structure and Efficient Use of Area with Electrostatic Discharge Protective Device Under the Pad Approach and Adjustment of via Configuration Thereto to Control Drain Junction Resistance
Application:
10/758,173 →
Memory Control Circuit, Memory Device, and Microcomputer
Application:
10/715,366 →
Control Circuit for Dc/Dc Converter
Application:
10/624,644 →
Undoped Oxide Liner/Bpsg for Improved Data Retention
Application:
10/617,450 →
Flash Memory Device
Application:
10/614,177 →
A Method for Manufacturing a Double Bitline Implant
Application:
10/431,321 →
Bmc-Hosted Real-Time Clock and Non-Volatile Ram Replacement
Application:
10/406,130 →
Non-Volatile Semiconductor Memory and Method of Manufacturing the Same
Application:
10/387,427 →
Dielectric Memory Cell Structure with Counter Doped Channel Region
Application:
10/342,549 →
Integrated Circuit Free from Accumulation of Duty Ratio Errors
Application:
10/335,925 →
System and Method for Y-Decoding in a Flash Memory Device
Application:
10/243,315 →
Method for Semiconductor Wafer Planarization by Isolation Material Growth
Application:
10/190,002 →
Semiconductor Device
Application:
10/090,822 →
A System for Generating a Main Clock Fom an Oscillation Signal Based Upon a Wakeup Signal of a Predetermined Cycle or Condition of the Oscillation Signal
Application:
09/939,751 →
Silicided Buried Bitline Process for a Non-Volatile Memory Cell
Application:
09/885,426 →