BMC-hosted real-time clock and non-volatile RAM replacement
View Patent ↗A baseboard management controller (BMC) hosts a real-time clock and non-volatile RAM replacement that does not require a battery power supply. The BMC includes an I/O mapped interface responsive to I/O accesses to an address range associated with storage locations of a real-time clock circuit and storage locations holding configuration information. The BMC receives power when a processor coupled to the BMC is not powered. The I/O address range may include 70 h and 71 h . A network interface may communicate information between a network external to the BMC and the real-time clock and/or the storage locations holding the configuration information. The network external to the BMC may communicate clock synchronization and/or configuration information to the BMC.
1. A baseboard management controller integrated circuit comprising:
an I/O mapped interface responsive to I/O accesses of a processor to an I/O address range associated with first storage locations of a real-time clock circuit and second storage locations holding configuration information; and
a network interface,
wherein the baseboard management controller integrated circuit is operable when other components of a system in which the baseboard management controller integrated circuit resides are in a powered-down state,
wherein at least a portion of the second storage locations resides on the baseboard management controller integrated circuit.
2. The baseboard management controller integrated circuit, as recited in claim 1 , wherein the network interface is coupled to communicate information between a network external to the baseboard management controller integrated circuit and at least one of the real-time clock circuit and the storage locations holding configuration information.
3. The baseboard management controller integrated circuit, as recited in claim 2 , wherein the information is real-time clock synchronization information.
4. The baseboard management controller integrated circuit, as recited in claim 1 , wherein the I/O mapped interface is responsive to I/O accesses of the processor to port 70 h and port 71 h.
5. The baseboard management controller integrated circuit, as recited in claim 1 , wherein at least a portion of the first storage locations resides on the baseboard management controller integrated circuit.
6. The baseboard management controller integrated circuit, as recited in claim 1 , wherein the baseboard management controller integrated circuit is Intelligent Platform Management Interface (IPMI) compliant.
7. The baseboard management controller integrated circuit, as recited in claim 1 , wherein the baseboard management controller integrated circuit is configured as a portion of a server within a server farm and is configured to monitor system parameters of the server.
8. The baseboard management controller integrated circuit, as recited in claim 1 , wherein the baseboard management controller integrated circuit is coupled to a power plane independent from the processor.
9. A computer system comprising:
a baseboard management controller circuit coupled to be powered when a processor coupled to the baseboard management controller circuit is not powered;
a remote computer coupled to the baseboard management controller circuit via a network interface;
wherein the baseboard management controller circuit includes an I/O mapped interface responsive to I/O accesses of the processor, the I/O accesses being to an I/O address range associated with first storage locations of a real-time clock circuit and second storage locations holding configuration information accessible through the I/O mapped interface; and
wherein the baseboard management controller circuit includes the network interface,
wherein at least a portion of the second storage locations reside on the remote computer.
10. The computer system, as recited in claim 9 , wherein the remote computer communicates clock synchronization information to the baseboard management controller circuit.
11. The computer system, as recited in claim 9 , wherein the remote computer communicates configuration information to the baseboard management controller circuit.
12. The computer system, as recited in claim 9 , wherein the I/O mapped interface is a port 70 h and port 71 h interface.
13. The computer system, as recited in claim 9 , further comprising:
a memory buffer wherein the memory buffer is nonvolatile memory and is coupled to receive configuration information from the baseboard management controller circuit.
14. The computer system, as recited in claim 13 , wherein the nonvolatile memory is a serial EEPROM.
15. A method for accessing a real-time clock and configuration information comprising:
executing, by a processor, an I/O command to access an I/O port associated with the real-time clock and configuration information, at least a portion of the configuration information being stored in storage locations residing on a baseboard management controller;
decoding the I/O command on a baseboard management controller; and
accessing the real-time clock coupled to the baseboard management controller.
16. The method, as recited in claim 15 , further comprising:
accessing, by the processor, the configuration information via the baseboard management controller.
17. The method, as recited in claim 15 , further comprising:
storing the real-time clock and at least a portion of the configuration information in non-volatile memory.
18. The method, as recited in claim 15 , further comprising:
supplying synchronization information to a plurality of computer systems, each having real-time clock circuits;
synchronizing the plurality of real-time clock circuits using the synchronization information.
19. The method, as recited in claim 18 , wherein the synchronization information is received by the baseboard management controller.
20. The method, as recited in claim 19 wherein the baseboard management controller is Intelligent Platform Management Interface (IPMI) compliant.
21. An apparatus comprising:
a baseboard management controller means for providing a port interface responsive to I/O access requests from a processor, the I/O access requests being for accessing real-time clock information and processor configuration information; and
means for providing a real-time clock;
wherein the baseboard management controller means comprises means for storing the processor configuration information; and
a network interface.
22. The apparatus, as recited in claim 21 , further comprising:
means for synchronizing the means for providing a real-time clock with a remote real-time clock.
23. A baseboard management controller integrated circuit comprising:
an I/O mapped interface responsive to I/O accesses of a processor to an I/O address range associated with first storage locations of a real-time clock circuit and second storage locations holding configuration information; and
a network interface,
wherein the baseboard management controller integrated circuit is operable when other components of a system in which the baseboard management controller integrated circuit resides are in a powered-down state,
wherein the baseboard management controller integrated circuit is configured to communicate with the processor and to communicate with a remote computer via the network interface, the remote computer being configured to receive system parameter information from the baseboard management controller.