Semiconductor device with core and periphery regions
View Patent ↗A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.
1. A semiconductor device, comprising:
a substrate having a core region and a periphery region;
a core dielectric layer formed over core region of the substrate and a periphery region dielectric layer formed over the periphery region of the substrate;
a conductive layer formed over the core region dielectric layer and the periphery region dielectric layer; and
a hard mask assembly formed over the conductive layer for patterning the conductive layer to have a first pattern in the core region that has conductive layer structures separated by a space and a second pattern in the periphery region that has at least one conductive layer structure, wherein the hard mask assembly includes:
a first hard mask layer patterned to define an opening corresponding to the space between conductive layer structures in the core region and the first hard mask layer disposed over the periphery region; and
a second hard mask layer conforming to the pattern of the first hard mask layer in the core region to laterally reduce the size of the opening corresponding to the space and patterned in the periphery region with the first hard mask layer to form a stack having a first hard mask structure and a second hard mask structure to mask the conductive layer structure of the periphery region.
2. The semiconductor device according to claim 1 , wherein the core region dielectric layer is a charge-trapping dielectric assembly.
3. The semiconductor device according to claim 1 , wherein the periphery region dielectric layer comprises a multiple layer gate dielectric layer.
4. The semiconductor device according to claim 2 , wherein the charge-trapping dielectric assembly includes:
a tunneling layer;
a charge-trapping layer; and
an insulating layer,
wherein the tunneling layer is disposed over the substrate, the charge-trapping layer is disposed over the tunneling layer and the insulating layer is disposed over the charge-trapping layer.
5. The semiconductor device according to claim 1 , wherein at least one of the core region dielectric layer and the periphery region dielectric layer includes a dielectric material having a permittivity greater than a permittivity of silicon oxide.
6. The semiconductor device according to claim 1 , wherein:
the space between conductive layer structures of the core region has a lateral dimension less than achievable by a resolution limit of lithography; and
the conductive layer structure of the periphery region has a lateral dimension achievable by lithography.
7. The semiconductor device according to claim 1 , further comprising an ARC between the first and second hard mask structures in the periphery region.
8. A semiconductor memory assembly having a core and a periphery formed by the device of claim 1 and comprising memory cells in the core having gates formed from the conductive layer structures of the core region and logic devices having gates formed from the at least one conductive layer structure of the periphery region.