Method and device for reducing interface area of a memory device
View Patent ↗A method and device for reducing interface area of a memory device. A poly-2 layer is formed above a substrate at an interface between a memory array and a periphery of the memory device. The poly-2 layer is etched proximate to the memory array. The poly-2 layer is etched proximate to the periphery such that a portion of the poly-2 layer remains at the interface.
1. A method for fabricating a memory device, said method comprising:
forming a poly-2 layer above a substrate at an interface between a memory array and a periphery of said memory device;
etching said poly-2 layer proximate to said memory array; and
etching said poly-2 layer proximate to said periphery such that a portion of said poly-2 layer remains at said interface.
2. The method as recited in claim 1 further comprising:
forming a poly-1 layer above said substrate at said interface, such that said poly-1 layer is above said substrate and beneath said poly-2 layer;
etching said poly-1 layer proximate to said memory array; and
etching said poly-1 layer proximate to said periphery such that a portion of said poly-1 layer remains at said interface.
3. The method as recited in claim 1 wherein said etching said poly-2 layer proximate to said memory array is accomplished by performing a stacked gate etch.
4. The method as recited in claim 1 wherein said etching said poly-2 layer proximate to said periphery is accomplished by performing a second gate etch.
5. The method as recited in claim 1 further comprising:
forming spacers proximate to said memory array; and
forming spacers proximate to said periphery.
6. The method as recited in claim 2 further comprising forming an ONO layer above said poly-1 layer such that said ONO layer is above said poly-1 layer and beneath said poly-2 layer.
7. The method as recited in claim 1 wherein said portion of said poly-2 layer remaining at said interface is a same height as said memory array proximate to said memory array a same height as said periphery proximate to said periphery, such that step size is smoothed out reducing an occurrence of stringers from spacer etching.
8. A method for fabricating a memory device, said method comprising:
forming a poly-1 layer above a substrate at an interface between a memory array and a periphery of said memory device;
forming a poly-2 layer above said poly-1 layer at said interface;
etching said poly-1 layer and said poly-2 layer proximate to said memory array; and
etching said poly-2 layer proximate to said periphery, such that an interface structure including a portion of said poly-1 layer and a portion of said poly-2 layer remains at said interface.
9. The method as recited in claim 8 wherein said etching said poly-1 layer and said poly-2 layer proximate to said memory array is accomplished by performing a stacked gate etch.
10. The method as recited in claim 8 wherein said etching said poly-2 layer proximate to said periphery is accomplished by performing a second gate etch.
11. The method as recited in claim 8 further comprising:
forming spacers proximate to said memory array; and
forming spacers proximate to said periphery.
12. The method as recited in claim 11 wherein said spacers are nitride spacers.
13. The method as recited in claim 8 further comprising forming an ONO layer above said poly-1 layer such that said ONO layer is above said poly-1 layer and beneath said poly-2 layer.
14. The method as recited in claim 8 wherein said interface structure is a same height as said memory array proximate to said memory array and a same height as said periphery proximate to said periphery, such that step size is smoothed out reducing an occurrence of stringers from spacer etching.