Semiconductor device and method for writing data into the semiconductor device
View Patent ↗A semiconductor device is provided which includes a memory part that includes memory cells having different threshold values; a read circuit that reads data from a memory cell to be programmed with write data that is input; and a detection circuit that compares the write data with the data read from the memory cell to thus detect a pattern in which programming of data causes erasing. The pattern that causes erasing during the programming is processed as an inhibited operation. If the inhibited operation is identified, the process is forcedly terminated without initiating the programming by the write command. This makes it possible to avoid erasing resulting from the programming.
1. A semiconductor device comprising:
a memory part that includes memory cells having different threshold values;
a read circuit that reads data from a memory cell to be programmed with write data that is input;
a detection circuit that compares the write data with the data read from the memory cell to thus detect a pattern in which programming of data causes erasing, further comprising a sense amplifier for verification, wherein the read circuit reads data from said memory cell by using the sense amplifier for verification so that the data read from said memory cell is compared with specific reference cells provided separate from reference cells for verification.
2. A semiconductor device comprising:
a memory part that includes memory cells having different threshold values;
a read circuit that reads data from a memory cell to be programmed with write data that is input;
a detection circuit that compares the write data with the data read from the memory cell to thus detect a pattern in which programming of data causes erasing, further comprising a sense amplifier for verification, wherein the read circuit reads data from said memory cell by using the sense amplifier for verification so that the data read from said memory cell is compared with reference cells for verification.
3. The semiconductor device as claimed in claim 2 , wherein the read circuit reads data from said memory cell twice through the sense amplifier for verification.
4. The semiconductor device as claimed in claim 2 , wherein the memory part includes banks that are simultaneously operable.
5. The semiconductor device as claimed in claim 2 , wherein:
the memory part includes banks that are simultaneously operable; and
the banks share the read circuit and the detection circuit.
6. The semiconductor device as claimed in claim 2 , wherein the sense amplifier for verification comprises a transistor circuit that shifts a read level at which data is read from said memory cell.
7. The semiconductor device as claimed in claim 2 , further comprising a circuit that outputs a result of detection by the detection circuit to an outside of the semiconductor device.
8. The semiconductor device as claimed in claim 2 , wherein the semiconductor device is a semiconductor memory device.
9. The semiconductor device as claimed in claim 2 , wherein the different threshold values are three or more different threshold values.
10. A semiconductor device comprising:
a memory part that includes memory cells having different threshold values;
a read circuit that reads data from a memory cell to be programmed with write data that is input;
a detection circuit that compares the write data with the data read from the memory cell to thus detect a pattern in which programming of data causes erasing, further comprising a sense amplifier for verification, wherein the read circuit reads data from said memory cell by using the sense amplifier for verification at a specific sense ratio different from that used for verification.