Integrated circuit free from accumulation of duty ratio errors
View Patent ↗An integrated circuit includes a first signal-inversion switching circuit which receives a signal supplied from an exterior thereof as a first input signal, followed by outputting the first input signal after logic inversion thereof in response to a first state of a switching signal and outputting the first input signal without logic inversion in response to a second state of the switching signal, a signal processing circuit which performs signal processing based on the output of the first signal-inversion switching circuit, and a second signal-inversion switching circuit which receives the output of the first signal-inversion switching circuit passing through the signal processing circuit as a second input signal, followed by outputting the second input signal after logic inversion thereof in response to the second state of the switching signal and outputting the second input signal without logic inversion in response to the first state of the switching signal.
1. An integrated circuit, comprising:
a first signal-inversion switching circuit having a first input node to receive a first input signal and a first output node to output an output signal, the first signal-inversion switching circuit configured to output an inversion of the first input signal at the first output node in response to a first state of a switching signal and to output the first input signal without logic inversion at the first output node in response to a second state of the switching signal;
a signal processing circuit which performs signal processing based on the output signal of said first signal-inversion switching circuit; and
a second signal-inversion switching circuit having a second input node to receive the output signal of said first signal-inversion switching circuit as a second input signal and a second output node to output an output signal, the second signal-inversion switching circuit configured to output an inversion of the second input signal at the second output node in response to the second state of the switching signal and to output the second input signal without logic inversion at the second output node in response to the first state of the switching signal.
2. The integrated circuit as claimed in claim 1 , wherein the first input signal is a clock signal, and said signal processing circuit includes:
a clock-control circuit which generates a timing control signal based on the output of said first signal-inversion switching circuit; and
a data-control circuit which acquires a data signal supplied from an exterior thereof in response to the timing control signal.
3. The integrated circuit as claimed in claim 2 , wherein said signal processing circuit further includes a circuit which generates and outputs a drive signal for driving a liquid-crystal-display panel based on the data signal acquired by said data-control circuit.
4. The integrated circuit as claimed in claim 2 , further comprising:
a third signal-inversion switching circuit which receives a signal supplied from an exterior thereof as a first input data signal, followed by outputting the first input data signal after logic inversion thereof to said data-control circuit in response to the first state of the switching signal and outputting the first input data signal without logic inversion to said data-control circuit in response to the second state of the switching signal; and
a forth signal-inversion switching circuit which receives the output of said third signal-inversion switching circuit as a second input data signal, followed by outputting the second input data signal after logic inversion thereof in response to the second state of the switching signal and outputting the second input data signal without logic inversion in response to the first state of the switching signal.
5. A liquid-crystal-display device, comprising:
a liquid-crystal-display panel;
a gate driver which drives gate-bus lines of said liquid-crystal-display panel; and
a plurality of data drivers which are arranged in cascade connection, and drive data-bus lines of said liquid-crystal-display panel,
wherein each of said data drivers receives a signal supplied from a preceding stage and transfers the signal to a following stage after inverting a logic thereof,
wherein each of said data drivers includes:
a first signal-inversion switching circuit having a first input node to receive a first input signal and a first output node to output an output signal, the first signal-inversion switching circuit configured to output an inversion of the first input signal at the first output node in response to a first state of a switching signal and to output the first input signal without logic inversion at the first output node in response to a second state of the switching signal;
a signal processing circuit which performs signal processing based on the output signal of said first signal-inversion switching circuit; and
a second signal-inversion switching circuit having a second input node to receive the output signal of said first signal-inversion switching circuit as a second input signal and a second output node to output an output signal, the second signal-inversion switching circuit configured to output an inversion of the second input signal at the second output node in response to the second state of the switching signal and to output the second input signal without logic inversion at the second output node in response to the first state of the switching signal.
6. The liquid-crystal-display device as claimed in claim 5 , wherein odd-number data drivers of said plurality of data drivers receive the switching signal being in the second state, and even-number data drivers of said plurality of data drivers receive the switching signal being in the first state.
7. A signal-transmission system, comprising:
a plurality of integrated circuits arranged in cascade connection,
wherein each of said integrated circuits receives a signal supplied from a preceding stage and transfers the signal to a following stage after inverting a logic thereof, and
wherein each of said integrated circuits includes:
a first signal-inversion switching circuit having a first input node to receive a first input signal and a first output node to output an output signal, the first signal-inversion switching circuit configured to output an inversion of the first input signal at the first output node in response to a first state of a switching signal and to output the first input signal without logic inversion at the first output node in response to a second state of the switching signal;
a signal processing circuit which performs signal processing based on the output signal of said first signal-inversion switching circuit; and
a second signal-inversion switching circuit having a second input node to receive the output signal of said first signal-inversion switching circuit as a second input signal and a second output node to output an output signal, the second signal-inversion switching circuit configured to output an inversion of the second input signal at the second output node in response to the second state of the switching signal and to output the second input signal without logic inversion at the second output node in response to the first state of the switching signal.
8. The signal-transmission system as claimed in claim 7 , wherein odd-number integrated circuits of said plurality of integrated circuits receive the switching signal being in the second state, and even-number integrated circuits of said plurality of integrated circuits receive the switching signal being in the first state.