Granted Patent B1

US 7,125,763 · App. 09/885,426 · Granted Oct 24, 2006

Abstract

Claims (19)

1. A process of fabricating a memory cell comprising a substrate that comprises a first region and a second region with a channel therebetween, the method comprising:

forming a gate above said channel of said substrate, wherein said gate comprises a single polysilicon layer;

forming bitlines on both sides of said gate subsequent to said forming said gate comprising said single polysilicon layer;

siliciding said bitlines;

forming a charge trapping region that contains a first amount of charge; and

forming a layer between said channel and said charge trapping region, wherein said layer has a thickness such that said first amount of charge is prevented from directly tunneling into said layer.

2. The process of claim 1 , comprising forming an oxide over said bitlines.

3. The process of claim 1 , comprising siliciding said single polysilicon layer.

4. The process of claim 3 , wherein said siliciding of said bitlines and said single polysilicon layer occur simultaneously.

5. The process of claim 1 , wherein said charge trapping region comprises silicon nitride.

6. The process of claim 1 , wherein said gate comprises an N-type material.

7. The process of claim 6 , wherein said gate comprises a polycrystalline silicon.

8. The process of claim 1 , further comprising forming an insulating layer on said charge trapping region.

9. The process of claim 8 , wherein said insulating layer comprises silicon dioxide.

10. The process of claim 9 , wherein said charge trapping region comprises silicon dioxide.

11. The process of claim 1 , wherein said memory cell comprises an EEPROM memory cell.

12. The process of claim 1 , wherein said memory cell comprises a two-bit memory cell.

13. The process of claim 1 , wherein said substrate comprises a P-type substrate.

14. The process of claim 1 , further comprising scaling the length of said bitlines.

Assignments (8)