Buried word line memory integrated circuit system
View Patent ↗An integrated circuit system includes providing a semiconductor substrate and forming buried word lines in the semiconductor substrate with the buried word lines including vertical charge-trapping dielectric layers. The system further includes forming bit lines further comprising forming in-substrate portions in the semiconductor substrate, and forming above-substrate portions over the semiconductor substrate.
1. An integrated circuit system comprising:
providing a semiconductor substrate;
forming buried word lines in the semiconductor substrate, the buried word lines including vertical charge-trapping dielectric layers;
forming bit lines further comprising:
forming in-substrate portions in the semiconductor substrate, and
forming above-substrate portions over the semiconductor substrate; and
forming conductive channels between the bit lines that are adjacent the charge-trapping dielectric layers.
2. The system as claimed in claim 1 further comprising forming the buried word lines and forming the bit lines to be connectible for single-density or double-density mode operation.
3. The system as claimed in claim 1 wherein the buried word lines further comprises:
forming conductive layers on the vertical charge-trapping dielectric layers; and
forming top dielectric barrier layers on the conductive layers.
4. The system as claimed in claim 1 wherein forming the in-substrate portions of the bit lines comprises implanting a dopant in the semiconductor substrate.
5. The system as claimed in claim 1 wherein forming the buried word lines comprises forming floating gates therein.
6. An integrated circuit system comprising:
providing a semiconductor substrate;
forming a first address line further comprising:
forming a charge-trapping dielectric layer vertically on a sidewall of a trench in the semiconductor substrate,
forming a conductive layer on the charge-trapping dielectric layer, and
forming a barrier dielectric over the conductive layer;
forming second address lines perpendicular to the first address line and partially in the semiconductor substrate to form dual bit locations; and
forming conductive channels between the second address lines that are adjacent the charge-trapping dielectric layers.
7. The system as claimed in claim 6 further comprising;
forming an additional address line perpendicular to the first address line operable therewith to form a plurality of dual bit locations at the intersection of the first and additional address lines.
8. The system as claimed in claim 6 wherein the first address line further comprises a further barrier layer under the conductive layer.
9. The system as claimed in claim 6 wherein forming the second address lines forms each second address line further comprising an in-substrate portion in the semiconductor substrate and an above-substrate portion on the semiconductor substrate in a dielectric layer.
10. The system as claimed in claim 6 further comprising forming a floating gate on the charge-trapping dielectric layer.