Non-volatile semiconductor memory and method of manufacturing the same
View Patent ↗A proposed non-volatile semiconductor memory and a method of manufacturing the same are directed to performing stable and highly reliable operations. First, grooves are formed in a p-type silicon semiconductor substrate, and impurity diffusion layers are formed on the bottom surfaces of the grooves. A gate insulating film is then formed on the p-type silicon semiconductor substrate. This gate insulating film has a three-layer structure in which a first insulating film made of a silicon oxide film, a charge capturing film made of a silicon nitride film, and a second insulating film made of a silicon oxide film, are laminated in this order. A gate electrode is then formed on the gate insulating film. A convexity formed by the grooves serves as the channel region of the non-volatile semiconductor memory. Even if the device size is reduced, an effective channel length can be secured in this non-volatile semiconductor memory. Thus, excellent stability and reliability can be achieved.
1. A non-volatile semiconductor memory comprising:
a semiconductor substrate having convexities;
a gate electrode;
a gate insulating film in which a charge capturing region is formed in the vicinities of the side walls of the convexities, the gate insulating film being formed between the semiconductor substrate and the gate electrode;
a pair of impurity diffusion layers at the bottoms of adjacent grooves that form the convexities of the semiconductor substrate, the pair of impurity diffusion layers serving as a source and a drain of a single memory cell transistor; and
a convex channel region formed in the side walls and upper surface of the convexities.
2. A non-volatile semiconductor memory comprising:
a semiconductor substrate having convexities;
a gate electrode;
a gate insulating film in which a charge capturing region is formed in the vicinities of the side walls of the convexities, the gate insulating film being formed between the semiconductor substrate and the gate electrode;
a pair of an impurity diffusion layers formed in adjacent ones of the convexities of the semiconductor substrate, the impurity diffusion layers serving as a source and a drain of a single memory cell transistor; and
a concave channel region formed in the side walls of the convexities and the bottom of a groove which forms the convexities.
3. The non-volatile semiconductor memory according to either claim 1 or claim 2 , wherein the gate insulating film includes a silicon nitride film.
4. The non-volatile semiconductor memory according to either claim 1 or claim 2 , wherein the film thickness of the gate insulating film on the upper surface of the convexities and/or the film thickness of the gate insulating film on the bottom surfaces of the grooves forming the convexities are greater than the film thickness of the gate insulating film in the vicinities of the side walls of the convexities.
5. The non-volatile semiconductor memory according to either claim 1 or claim 2 , wherein a charge capturing rate of the gate insulating film in the vicinities of the side walls of the convexity is higher than a charge capturing rate of the gate insulating film on the upper surface of the convexity and/or a charge capturing rate of the gate insulating film on the bottom surfaces of the grooves that form the convexity.