IP Library Granted Patent US 7,038,950
Granted Patent B1
US 7,038,950 · App. 10/982,296 · Granted May 2, 2006

Multi bit program algorithm

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Quick Facts
Patent No.
US 7,038,950
App. No.
10/982,296
Granted
May 2, 2006
Kind
B1
Abstract

Methods of programming NEW data into unprogrammed bits of a group of memory cells is provided. The method applies an interactive programming algorithm that individually verifies and programs the NEW data, reference (REF) data, and existing or OLD data. OLD data is separately verified to a compensated program verify level from that of the NEW data to improve memory reliability and insure minimal uniform stress levels to the array. The improved programming algorithm prevents older data from being needlessly refreshed, thus mitigating stress to the cells that eventually causes the data areas to decay at different rates and become prematurely unreliable.

Claims (46)

1. A method of programming NEW data into unprogrammed bits of a group of memory cells, the group comprising the unprogrammed bits and programmed bits having OLD data, the method comprising:

pre-reading the group of cells to identify and exclude from NEW data programming operations all addresses of the programmed memory bits having OLD data;

verifying a programming operation on the unprogrammed memory bits by identifying whether a PV_New voltage level of the unprogrammed bits generally corresponds to the NEW data;

performing a programming operation on the group of unprogrammed memory bits until it is determined that the PV_New voltage level generally corresponds to the NEW data;

verifying a programming operation on a group of reference bits having REF data associated with the NEW and OLD data by identifying whether a PV_refresh_ref voltage level of the reference cells generally corresponds to the REF data;

reading the OLD data if it is determined that the PV_refresh_ref voltage level of the reference cells does not generally correspond to the REF data;

performing a programming operation on the group of reference cells until it is determined that the PV_refresh_ref voltage level of the reference cells generally corresponds to the REF data;

providing a compensated PV_refresh voltage level based on the PV_refresh_ref voltage level and a functional relationship between the NEW data and the OLD data;

verifying a programming operation on the programmed memory bits by identifying whether the PV_refresh voltage level of the cells generally corresponds to the OLD data; and

performing a programming operation on the group of programmed memory bits until it is determined that the PV_refresh voltage level generally corresponds to the OLD data.

2. The method of claim 1 , wherein pre-reading the group of cells to identify and exclude from NEW data programming operations all addresses of the programmed memory bits having OLD data comprises:

reading a current memory bit from the group of memory cells;

determining whether the current memory bit has been programmed based on whether OLD data was read from the current bit;

excluding the current bit if OLD data was read from the current bit;

determining whether all bits have been excluded from the group of memory cells and if OLD data was read from the current bit;

executing a program/erase cycle if it has been determined that all bits have been excluded from the group of memory cells;

incrementing the current bit address if it was determined that all bits have not been excluded from the group of memory cells, and continuing reading other bits of the group of memory cells;

determining whether the last address of the group of memory cells has been achieved, if it has been determined that the current memory bit has not been programmed based on whether OLD data was read from the current bit; and

incrementing the current bit address if it was determined that the last address of the group of memory cells has not been achieved.

3. The method of claim 1 , wherein the memory cells have one or more physical bits per cell, and the bits have two or more data states corresponding to two or more threshold voltage values.

4. The method of claim 1 , further comprising:

determining whether the NEW data is blank subsequent to verifying a programming operation on the unprogrammed memory bits by identifying whether a PV_New voltage level of the unprogrammed bits generally corresponds to the NEW data;

performing a programming operation on the group of unprogrammed memory bits if it is determined that the New data is not blank, until it is determined that the PV_New voltage level generally corresponds to the NEW data; and

performing a programming operation on the group of programmed memory bits containing OLD data if it is determined that the New data is blank, until it is determined that the PV_refresh voltage level generally corresponds to the OLD data.

5. The method of claim 1 , wherein the providing a compensated PV_refresh voltage level based on the PV_refresh_ref voltage level and a functional relationship between the NEW data and the OLD data comprises computing a “1” to “0” ratio of the OLD and NEW data represented by the REF cells.

6. The method of claim 1 , wherein the functional relationship between the population of the NEW data and the OLD data, further comprises an OLD and a NEW weighting factor generally corresponding to the OLD and NEW data.

7. The method of claim 1 , wherein the programming operation on the group of unprogrammed memory bits comprises:

applying programming pulses until a desired program verify voltage level PV_New corresponding to a desired threshold voltage value of the bits having a desired NEW data state is achieved.

8. The method of claim 1 , wherein the programming operation on the group of reference cells comprises:

applying programming pulses until a desired program verify voltage level PV_refresh_ref corresponding to a desired threshold voltage value of the cells having a desired REF data state is achieved.

9. The method of claim 1 , wherein the programming operation on the group of programmed memory bits, to refresh the OLD data comprises:

applying programming pulses until a desired program verify voltage level PV_refresh corresponding to a desired threshold voltage value of the bits having a desired OLD data state is achieved.

10. The method of claim 1 , wherein the program verify voltage level PV_New corresponding to the NEW data is substantially the same voltage level as the program verify voltage level PV_refresh corresponding to the OLD data.

11. The method of claim 1 , wherein the program verify voltage level PV_New corresponding to the NEW data is substantially the same voltage level as the program verify voltage level PV_refresh_ref corresponding to the REF data and the program verify voltage level PV_refresh corresponding to the OLD data.

12. The method of claim 1 , wherein the program verify voltage level PV_New corresponding to the NEW data is a different voltage level than the program verify voltage level PV_refresh corresponding to the OLD data.

13. The method of claim 1 , wherein the providing a compensated PV_refresh voltage level based on the PV_refresh_ref voltage level and a functional relationship between the NEW data and the OLD data comprises computing a PV_refresh voltage level generally conforming to the relationship:

PV _refresh= PV _refresh — ref*Vt — avg _New/ Vt — avg _Old

wherein Vt_avg_New generally corresponds to the average threshold voltage level of the NEW data, and wherein Vt_avg_Old generally corresponds to the average threshold voltage level of the OLD data before the OLD data is refreshed.

14. The method of claim 1 , further comprising pre-programming a portion of the memory cells prior to pre-reading the group of memory cells.

15. The method of claim 1 , wherein the programming operations increase the threshold voltage values generally corresponding to bits of respective memory cells of the group.

16. The method of claim 1 , wherein different portions of the group of memory cells are initially programmed to different threshold voltage values.

17. The method of claim 1 , wherein the group of memory cells comprises a portion of a larger array of memory cells, wherein different portions of the array of memory cells are initially programmed to different threshold voltage values.

18. The method of claim 1 , wherein one or more gate and drain voltages used in the verify and program operations are adjusted to further optimize the method.

19. The method of claim 1 , wherein the cells are multi-level bit cells, and the program verify levels represent a plurality of program verify levels per bit, and wherein each corresponding PV_refresh level is compensated for verification of the OLD data.

20. The method of claim 1 , wherein multiple groups of memory cells of the array are programmed.

21. The method of claim 1 , wherein the group of memory cells comprises a portion of an array of memory cells.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →