IP Library Granted Patent US 7,196,379
Granted Patent B2
US 7,196,379 · App. 10/965,856 · Granted Mar 27, 2007

MOS capacitor device

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Quick Facts
Patent No.
US 7,196,379
App. No.
10/965,856
Granted
Mar 27, 2007
Kind
B2
Abstract

A semiconductor device in which a dielectric breakdown of a gate oxide in a MOS capacitor can be prevented and in which a circuit area can be reduced. The semiconductor device comprises an NMOS transistor a gate of which is connected to a terminal VDD on a high potential side and a PMOS transistor a gate of which is connected to a terminal GND on a low potential side, source/drain (S/D) regions of the NMOS transistor and source/drain (S/D) regions of the PMOS transistor being electrically connected.

Claims (9)

1. A semiconductor device having MOS transistors which function as capacitors, the device comprising:

an n-channel MOS transistor a gate of which is connected to a terminal on a high potential side wherein a first MOS capacitor is formed; and

a p-channel MOS transistor a gate of which is connected to a terminal on a low potential side wherein a second MOS capacitor is formed, wherein

the first and second MOS capacitors are connected in series,

source/drain regions of the n-channel MOS transistor and source/drain regions of the p-channel MOS transistor are electrically connected,

parasitic diodes formed between the source/drain regions of the n-channel MOS transistor and a substrate region thereof and parasitic diodes formed between the source/drain regions of the p-channel MOS transistor and a substrate region thereof are electrically connected,

the substrate region of the n-channel MOS transistor is connected to a terminal on the low potential side, and the substrate region of the p-channel MOS transistor is connected to a terminal on the high potential side, and

a direct current path from a high-potential-side terminal through the parasitic diodes of the n-channel MOS transistor and the parasitic diodes of the p-channel MOS transistor to a low-potential-side terminal is formed.

2. The semiconductor device according to claim 1 , wherein an intermediate potential between the MOS capacitors is a potential between the parasitic diodes formed in the n-channel MOS transistor and the parasitic diodes formed in the p-channel MOS transistor which are electrically connected.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036038/0467 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024982/0245 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021998/0645 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2004
From: MORISHITA, TOMONARI; NUNOKAWA, HIDEO; TACHIBANA, SUGURU; KIHARA, FUKUJI
To: FUJITSU LIMITED
Reel/Frame 015899/0823 →