Semiconductor memory devices and methods for fabricating the same

1. A method for fabricating a dual-bit memory device comprising the steps of:

providing a semiconductor substrate;

forming a tunnel oxide overlying said semiconductor substrate;

forming first and second spaced apart disposable structures overlying said semiconductor substrate and exposing a portion of said tunnel oxide, each of said first and second disposable structures having a vertical edge;

forming a first floating gate on said vertical edge of said first disposable structure and a spaced apart second floating gate on said vertical edge of said second disposable structure;

forming an interlayer dielectric overlying said first floating gate and said second floating gate;

forming a control gate between said first floating gate and said spaced apart second floating gate and contacting said interlayer dielectric; and

removing the first and second spaced apart disposable spacers.

2. The method of claim 1 , wherein the step of forming an interlayer dielectric overlying said first floating gate and said second floating gate comprises forming said interlayer dielectric in contact with said tunnel oxide.

3. The method of claim 1 , wherein the step of forming an interlayer dielectric comprises the steps of:

forming a first silicon oxide layer overlying said first floating gate and said second floating gate;

depositing a silicon nitride layer overlying said first silicon oxide layer; and

depositing a second silicon oxide layer overlying said silicon nitride layer.

4. The method of claim 1 , wherein the step of forming said first and second spaced apart disposable structures comprises the step of forming first and second spaced apart silicon nitride structures.

5. The method of claim 1 , further comprising the steps of:

forming an impurity-doped region in said semiconductor substrate; and

forming an electrical contact on said impurity-doped region.

6. The method of claim 1 , wherein the step of forming said first and second floating gates comprises the step of forming substantially vertical first and second floating gates.

7. The method of claim 1 , wherein the step of removing said first and second spaced apart disposable spacers comprises the step of etching said first and second spaced apart disposable spacers using reactive ion etching.

8. The method of claim 1 , wherein, after the step of removing said first and second spaced apart disposable spacers, a spacer is formed on said first and second floating gates.

9. A method for fabricating a semiconductor device, the method comprising the steps of:

depositing a first material layer overlying a semiconductor substrate;

etching said first material layer to form a first material member and a second material member;

exposing portions of said semiconductor substrate between said first and second material members;

forming a tunnel oxide layer on said exposed portions of said semiconductor substrate;

depositing a first silicon layer overlying said first and second material members and said tunnel oxide layer;

anisotropically etching said first silicon layer to form a first floating gate disposed adjacent a side of said first material member and a second floating gate disposed adjacent a side of said second material member, said first floating gate discontinuous with said second floating gate;

forming an interlevel dielectric layer overlying said tunnel oxide layer, said first and second floating gates, and said first and second material members;

depositing a second silicon layer overlying said interlevel dielectric layer;

removing a portion of said second silicon layer and a portion of said interlevel dielectric layer to expose said first and second material members;

anisotropically etching said first and second material members, and forming a first metal silicide contact on said second silicon layer.

10. The method of claim 9 , further comprising the steps of;

forming an impurity-doped region in said semiconductor substrate in self alignment with said first floating gate; and

forming a second metal silicide contact on said impurity-doped region.

11. The method of claim 9 , wherein the step of depositing a first material layer overlying said semiconductor substrate comprises the step of depositing a silicon nitride layer overlying said semiconductor substrate.

12. The method of claim 9 , wherein the step of forming an interlevel dielectric layer comprises the steps of:

forming a first silicon oxide layer overlying said tunnel oxide layer, said first and second floating gates, and said first and second material members;

depositing a silicon nitride layer on said first silicon oxide layer; and

forming a second silicon oxide layer overlying said silicon nitride layer.

13. The method of claim 9 , wherein, before the step of etching said first material layer to form first and second material members, the method further comprises the steps of:

etching a trench that extends through said first material layer and into said semiconductor substrate; and

depositing an insulating dielectric material in said trench.

14. The method of claim 13 , wherein, before the step of etching a trench, the method comprises the steps of:

depositing a first photoresist mask on said first material layer; and

removing a portion of said first photoresist mask according to a first pattern.

15. The method of claim 14 , wherein, before the step of etching said first material layer to form first and second material members, the method comprises the steps of:

depositing a second photoresist mask on said first material layer; and

removing a portion of said second photoresist mask according to a second pattern that is perpendicular to said first pattern.