Method of making a memory cell
View Patent ↗Methods of making memory devices/cells are disclosed. First and second electrode layers and a controllably conductive media therebetween are formed over a dielectric layer that has a planar surface and at least one opening. The layers on the dielectric layer planar surface are removed so that the remaining second electrode surface in the opening is co-planar with the dielectric layer planar surface. Methods of using the memory devices/cells, and devices such as computers containing the memory devices/cells are also disclosed.
1. A method of making a memory cell for a non-volatile semiconductor device, comprising:
providing a dielectric layer having a planar surface and at least one opening formed therein;
forming a first electrode layer over the dielectric layer planar surface and in the opening;
forming a controllably conductive media comprising an active layer and a passive layer over the first electrode and in the opening, the active layer having at least two relatively stable oxidation states and comprising at least one of a chalcogenide, transition metal oxide, and an organic semiconductor material, the passive layer comprising at least one conductivity-facilitating compound having at least two relatively stable oxidation states, wherein the passive layer and the active layer are selected so that energy bands of the two relatively stable oxidation states of the passive layer match with energy bands of the two relatively stable oxidation states of the active layer;
forming a second electrode layer over the controllably conductive media and in the opening; and
removing the first and second electrode layers and controllably conductive media on the dielectric layer planar surface so that the remaining second electrode surface in the opening is co-planar with the dielectric layer planar surface.
2. The method of claim 1 , wherein removing is carried out by chemical mechanical polishing.
3. The method of claim 1 , wherein the active layer comprises at least one selected from the group consisting of polyacetylene; polydiphenylacetylene; poly(t-butyl)diphenylacetylene; poly(trifluoromethyl)diphenylacetylene; polybis(trifluoromethyl)acetylene; polybis(t-butyldiphenyl)acetylene; poly(trimethylsilyl) diphenylacetylene; poly(carbazole)diphenylacetylene; polydiacetylene; polyphenylacetylene; polypyridineacetylene; polymethoxyphenylacetylene; polymethylphenylacetylene; poly(t-butyl)phenylacetylene; polynitro-phenylacetylene; poly(trifluoromethyl) phenylacetylene; poly(trimethylsilyl)pheylacetylene; polydipyrrylmethane; polyindoqiunone; polydihydroxyindole; polytrihydroxyindole; furane-polydihydroxyindole; polyindoqiunone-2-carboxyl; polyindoqiunone; polybenzobisthiazole; poly(p-phenylene sulfide); polyaniline; polythiophene; polypyrrole; polysilane; polystyrene; polyfuran; polyindole; polyazulene; polyphenylene; polypyridine; polybipyridine; polyphthalocyanine; polysexithiofene; poly(siliconoxohemiporphyrazine); poly(germaniumoxohemiporphyrazine); poly(ethylenedioxythiophene); polymetallocene complexes; and polypyridine metal complexes.
4. The method of claim 1 , wherein the first electrode layer comprises at least copper.
5. The method of claim 4 , wherein the passive layer comprises at least copper sulfide.
6. The method of claim 5 , wherein the passive layer comprising at least copper sulfide is formed by contacting a sulfide compound with the first electrode.
7. The method of claim 6 , wherein the sulfide compound is contacted with the first electrode for a time about 1 second to about 60 minutes at a temperature from about 15° C. to about 500° C.
8. A method of preventing formation of voids at interfaces between layers in a memory cell structure of a non-volatile semiconductor device, comprising:
providing a first electrode over a dielectric layer having at least one opening;
forming a passive layer over the first electrode and in the opening, wherein a element of the passive layer is not contacted with an interface between the first electrode and the dielectric layer in an area of the memory cell;
forming an active layer over the passive layer and in the opening;
forming a second electrode layer over the active layer and in the opening; and
planarizing the structure, the active layer having at least two relatively stable oxidation states and comprising at least one of a chalcogenide, transition metal oxide, and an organic semiconductor material, the passive layer comprising at least one conductivity-facilitating compound having at least two relatively stable oxidation states, wherein the passive layer and the active layer are selected so that energy bands of the two relatively stable oxidation states of the passive layer match with energy bands of the two relatively stable oxidation states of the active layer.
9. The method of claim 8 , wherein a element of the active layer is not contacted with interfaces between layers of the passive layer, first electrode, and dielectric in the area of the memory cell.
10. The method of claim 8 , wherein planarizing is carried out by chemical mechanical polishing.
11. The method of claim 8 , wherein the active layer comprises at least one selected from the group consisting of polyacetylene; polydiphenylacetylene; poly(t-butyl)diphenylacetylene; poly(trifluoromethyl)diphenylacetylene; polybis(trifluoromethyl)acetylene; polybis(t-butyldiphenyl)acetylene; poly(trimethylsilyl) diphenylacetylene; poly(carbazole)diphenylacetylene; polydiacetylene; polyphenylacetylene; polypyridineacetylene; polymethoxyphenylacetylene; polymethylphenylacetylene; poly(t-butyl)phenylacetylene; polynitro-phenylacetylene; poly(trifluoromethyl) phenylacetylene; poly(trimethylsilyl)pheylacetylene; polydipyrrylmethane; polyindoqiunone; polydihydroxyindole; polytrihydroxyindole; furane-polydihydroxyindole; polyindoqiunone-2-carboxyl; polyindoqiunone; polybenzobisthiazole; poly(p-phenylene sulfide); polyaniline; polythiophene; polypyrrole; polysilane; polystyrene; polyfuran; polyindole; polyazulene; polyphenylene; polypyridine; polybipyridine; polyphthalocyanine; polysexithiofene; poly(siliconoxohemiporphyrazine); poly(germaniumoxohemiporphyrazine); poly(ethylenedioxythiophene); polymetallocene complexes; and polypyridine metal complexes.
12. The method of claim 8 , wherein the first electrode layer comprises at least copper.
13. The method of claim 12 , wherein the passive layer comprises at least copper sulfide.
14. The method of claim 13 , wherein the passive layer comprising at least copper sulfide is formed by contacting a sulfide compound with the first electrode.
15. The method of claim 14 , wherein the sulfide compound is contacted with the first electrode for a time about 1 second to about 60 minutes at a temperature from about 15° C. to about 500° C.
16. A method of making a memory cell for a non-volatile semiconductor device, comprising:
providing a dielectric layer having a planar surface and at least one opening formed therein;
forming a continuous and conformal first electrode layer over the dielectric layer planar surface and in the opening;
forming a controllably conductive media comprising an active layer and a passive layer over the first electrode and in the opening, the controllably conductive media can be rendered conductive, non-conductive or any state therebetween in a controllable manner by an external stimulus, the active layer having at least two relatively stable oxidation states and comprising at least one of a chalcogenide, transition metal oxide, and an organic semiconductor material, the passive layer comprising at least one conductivity-facilitating compound having at least two relatively stable oxidation states, wherein the passive layer and the active layer are selected so that energy bands of the two relatively stable oxidation states of the passive layer match with energy bands of the two relatively stable oxidation states of the active layer;
forming a second electrode layer over the controllably conductive media and in the opening; and
removing the first and second electrode layers and controllably conductive media on the dielectric layer planar surface so that the remaining second electrode surface in the opening is co-planar with the dielectric layer planar surface.
17. The method of claim 16 , wherein a element of the active layer is not contacted with interfaces between layers of the passive layer, first electrode, and dielectric in the area of the memory cell.
18. The method of claim 16 , wherein planarizing is carried out by chemical mechanical polishing.
19. The method of claim 16 , wherein the active layer comprises at least one selected from the group consisting of polyacetylene; polydiphenylacetylene; poly(t-butyl)diphenylacetylene; poly(trifluoromethyl)diphenylacetylene; polybis(trifluoromethyl)acetylene; polybis(t-butyldiphenyl)acetylene; poly(trimethylsilyl) diphenylacetylene; poly(carbazole)diphenylacetylene; polydiacetylene; polyphenylacetylene; polypyridineacetylene; polymethoxyphenylacetylene; polymethylphenylacetylene; poly(t-butyl)phenylacetylene; polynitro-phenylacetylene; poly(trifluoromethyl) phenylacetylene; poly(trimethylsilyl)pheylacetylene; polydipyrrylmethane; polyindoqiunone; polydihydroxyindole; polytrihydroxyindole; furane-polydihydroxyindole; polyindoqiunone-2-carboxyl; polyindoqiunone; polybenzobisthiazole; poly(p-phenylene sulfide); polyaniline; polythiophene; polypyrrole; polysilane; polystyrene; polyfuran; polyindole; polyazulene; polyphenylene; polypyridine; polybipyridine; polyphthalocyanine; polysexithiofene; poly(siliconoxohemiporphyrazine); poly(germaniumoxohemiporphyrazine); poly(ethylenedioxythiophene); polymetallocene complexes; and polypyridine metal complexes.
20. The method of claim 16 , wherein the first electrode layer comprises at least copper.
21. The method of claim 16 , wherein the passive layer comprises at least copper sulfide.
22. The method of claim 16 , wherein the passive layer and the active layer are formed in a manner so as to prevent void formation in the first electrode layer.