SONOS memory with inversion bit-lines
View Patent ↗A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.
1. A SONOS memory cell formed on a semiconductor substrate, comprising:
a bottom dielectric disposed on the semiconductor substrate;
a top dielectric disposed on portions of the bottom dielectric;
a word-line gate structure disposed on the top dielectric, a portion of the semiconductor substrate disposed under the word-line gate forming a channel region;
at least one bit-line gate for inducing at least one inversion bit-line to a side of the channel region within the semiconductor substrate; and
at least one charge trapping structure formed to be electrically isolated by being surrounded by the top and bottom dielectrics between a sidewall of the bit-line gate and a sidewall of the word-line gate structure.
2. The SONOS memory cell of claim 1 , wherein the at least one bit-line gate includes:
a first bit-line gate for inducing a source inversion bit-line to a first side of the channel region within the semiconductor substrate such that a junction is not formed for the source bit-line; and
a second bit-line gate for inducing a drain inversion bit-line to a second side of the channel region within the semiconductor substrate such that a junction is not formed for the drain bit-line.
3. The SONOS memory cell of claim 2 , wherein the at least one bit-line gate further includes:
a third bit-line gate disposed between the first and second bit-line gates for inducing a conductive path from the first inversion bit-line to the second inversion bit-line, during source side injection programming.
4. The SONOS memory cell of claim 2 , further comprising:
a first charge trapping structure electrically isolated and disposed between sidewalls of the first bit-line gate and the word-line gate structure; and
a second charge trapping structure electrically isolated and disposed between sidewalls of the second bit-line gate and the word-line gate structure.
5. The SONOS memory cell of claim 1 , wherein at least one of the top dielectric, the charge trapping structure, and the bottom dielectric is comprised of a respective high-k dielectric material having a dielectric constant higher than that of silicon dioxide (SiO 2 ).
6. The SONOS memory cell of claim 1 , further comprising:
a contact junction formed under a portion of the bit-line gate that is outside of a core region of a memory device comprised of the SONOS memory cell.
7. The SONOS memory cell of claim 1 , wherein the charge trapping structure is comprised of a nano-crystal material.
8. A SONOS memory cell formed on a semiconductor substrate, comprising:
a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material;
a word-line gate structure disposed on the top dielectric, a portion of the semiconductor substrate disposed under the word-line gate forming a channel region; and
at least one bit-line gate filling a trench formed into the semiconductor substrate, each bit-line gate inducing an inversion bit-line at sidewalls of the trench within the semiconductor substrate.
9. The SONOS memory cell of claim 8 , wherein the at least one bit-line gate includes:
a first bit-line gate filling a first trench formed into the semiconductor substrate, the first bit-line gate inducing a source inversion bit-line at sidewalls of the first trench within the semiconductor substrate such that a junction is not formed for the source bit-line; and
a second bit-line gate filling a second trench formed into the semiconductor substrate, the second bit-line gate inducing a drain inversion bit-line at sidewalls of the second trench within the semiconductor substrate such that a junction is not formed for the drain bit-line.
10. The SONOS memory cell of claim 8 , wherein at least one of the top dielectric, the charge trapping material, and the bottom dielectric is comprised of a respective high-k dielectric material having a dielectric constant higher than that of silicon dioxide (SiO 2 ).
11. The SONOS memory cell of claim 8 , further comprising:
a contact junction formed under a portion of the bit-line gate that is outside of a core region of a memory device comprised of the SONOS memory cell.
12. The SONOS memory cell of claim 8 , wherein the charge trapping material is comprised of a nano-crystal material.
13. A SONOS memory cell formed on a semiconductor substrate, comprising:
a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material;
a word-line gate structure disposed on the top dielectric, a portion of the semiconductor substrate disposed under the word-line gate forming a channel region;
a first bit-line gate for inducing a source inversion bit-line to a first side of the channel region within the semiconductor substrate such that a junction is not formed for the source bit-line;
a second bit-line gate for inducing a drain inversion bit-line to a second side of the channel region within the semiconductor substrate such that a junction is not formed for the drain bit-line; and
a third bit-line gate disposed between the first and second bit-line gates for inducing a conductive inversion path from the first inversion bit-line to the second inversion bit-line, during source side injection programming.
14. The SONOS memory cell of claim 13 , wherein the charge trapping material includes:
a first charge trapping structure electrically isolated and disposed at a first sidewall of the word-line gate structure; and
a second charge trapping structure electrically isolated and disposed at a second sidewall of the word-line gate structure.
15. The SONOS memory cell of claim 14 , wherein each of the bit-line gates is formed within a respective trench of the semiconductor substrate.
16. The SONOS memory cell of claim 13 , wherein the word-line gate structure is formed within a trench of the semiconductor substrate.
17. The SONOS memory cell of claim 13 , wherein at least one of the top dielectric, the charge trapping material, and the bottom dielectric is comprised of a respective high-k dielectric material having a dielectric constant higher than that of silicon dioxide (SiO 2 ).
18. The SONOS memory cell of claim 13 , wherein the charge trapping material is a charge trapping structure that is electrically isolated and disposed along a side of the word-line gate structure.
19. The SONOS memory cell of claim 13 , further comprising:
a contact junction formed under a portion of the bit-line gate that is outside of a core region of a memory device comprised of the SONOS memory cell.
20. The SONOS memory cell of claim 13 , wherein the charge trapping material is comprised of a nano-crystal material.