Disposable hard mask for memory bitline scaling
View Patent ↗The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.
1. A method of manufacturing a semiconductor memory device, the method comprising the steps of:
forming a charge trapping layer over a substrate;
forming a patterned hard mask layer over the charge trapping layer;
forming doped regions of a first conductivity type in the substrate by implanting ion species through the charge trapping layer using the hard mask layer to define an implant pattern of the doped regions;
laterally diffusing the doped regions into the substrate; and
forming buried bitlines of a second conductivity type in the doped regions and the substrate by implanting ion species through the charge trapping layer using the hard mask layer to define an implant pattern of the bitlines so that the forming and diffusing steps result in laterally diffused doped regions adjacent each buried bitline that inhibit a leakage current between adjacent pairs of buried bitlines through substrate regions disposed between the diffused doped regions.
2. The method according to claim 1 , further including the step of:
defining at least two regions in the charge trapping layer for programming and erasing the semiconductor device.
3. The method according to claim 1 , further including the step of:
forming a conductive layer over the charge trapping layer,
wherein the charge trapping layer is interposed between the substrate and the conductive layer.
4. The method according to claim 1 , wherein the charge trapping layer is part of a multi-layer dielectric layer.
5. The method according to claim 4 , wherein the multi-layer dielectric layer includes a charge trapping dielectric layer as the charge trapping layer.
6. The method according to claim 5 , wherein the multi-layer dielectric layer is an oxide-nitride-oxide (ONO) layer.
7. The method according to claim 1 , wherein the charge trapping layer is a charge trapping dielectric layer disposed over a tunneling layer and disposed under an insulating layer.
8. The method according to claim 7 , wherein a material of the tunneling layer is one or more of a SiO 2 or an oxynitride.
9. The method according to claim 8 , wherein the charge trapping layer includes one or more materials of a permittivity greater than SiO 2 .
10. The method according to claim 9 , wherein the one or more materials of the charge trappling layer are one or more of, silicon nitride (Si x N y ), silicon oxynitride (SiO x N y ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO), zirconium oxide (ZrO), titanium oxide (TiO), yttrium oxide (YO), zirconium silicate, hafnium silicate, lanthanum oxide (La 2 O 3 ), cerium oxide (CeO 2 ), bismuth silicon oxide (Bi 4 Si 2 O 12 ), tantalum oxide (Ta 2 O 5 ), tungsten oxide (WO 3 ), LaAlO 3 , BST (Ba 1-x Sr x TiO 3 ), PbTiO 3 , BaTiO 3 , SiTiO 3 , PbZrO 3 , PST (PbSc x Ta 1-x O 3 ), PZN (PbZn x Nb 1-x O 3 ), PZT (PbZr x Ti 1-x O 3 ), or PMN (PbMg x Nb 1-x O 3 ).
11. The method according to claim 1 , wherein the hard mask layer is patterned by depositing and patterning a photoresist layer over the hard mask layer to form a pattern in the photoresist; and transferring the pattern from the photoresist to the hard mask layer.
12. The method according to claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.
13. The method according to claim 1 , further including the steps of:
forming an insulating layer that fills apertures in the hard mask layer.
14. The method according to claim 13 , further including the step of:
removing the hard mask layer.
15. The method according to claim 1 , further including the step of:
annealing the semiconductor device to repair damage in the charge trapping layer due to the implanting of the ions to form the doped regions.
16. The method according to claim 1 , wherein the charge trapping layer is a conducting layer.
17. The method according to claim 1 , further including the step of:
forming a control gate over the charge trapping layer.
18. The method according to claim 17 , further including the step of:
forming a multi-layer dielectric layer over the charge trapping layer,
wherein the multi-layer dielectric layer is interposed between the charge trapping layer and the control gate.
19. The method according to claim 1 , wherein forming the buried bitlines damages the charge trapping layer and the method further comprises forming a conductive wordline over the charge trapping layer that does not have substantial coupling to the damaged portions of the charge trapping layer.